ARMv8指令集详解：新A64指令与A32、T32扩展

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"ARMv8指令集是ARM架构的最新版本，主要引入了64位的A64指令集，应用于AArch64状态，同时也对A32和T32指令集进行了扩展，以适应AArch32状态的需求。这份文档提供了一个高层的概述，详细阐述了ARMv8指令集的主要特性、新指令以及推荐的架构级汇编语言表示法。" ARMv8指令集是ARM公司在其处理器架构上的重大更新，主要目标是引入对64位计算的支持。在这个版本中，最显著的变化是引入了A64指令集，这是专门为64位计算环境设计的新指令集，适用于AArch64状态，它显著增强了处理能力和效率，特别是在大数据、云计算和移动设备的高性能计算领域。在AArch64状态下，A64指令集提供了大量的新指令，优化了内存访问、算术运算、分支控制等操作，使其能够更好地处理复杂的计算任务。此外，A64指令集采用了更紧凑的编码方式，降低了指令长度，提高了代码密度，有利于缓存效率和执行速度。同时，为了保持与现有的32位软件的兼容性，ARMv8也对A32和T32指令集进行了扩展。A32指令集通常用于传统的ARM模式，而T32（Thumb-2）是其节能版本，提供了更高效的编码。在ARMv8中，这些指令集增加了新的指令，以支持更多的64位数据处理，尽管它们仍然主要用于32位环境。文档中提到的“首选的架构级汇编语言表示法”是指为A64指令集定义的一种标准汇编语法，它是程序员编写汇编代码时使用的符号表示，确保了代码的可读性和可移植性。这种表示法规定了如何用文本形式来表示A64指令，使得开发人员可以更加直观地理解和编写针对ARMv8架构的程序。除了上述内容，ARMv8指令集还包含了其他关键特性，如向量处理单元（NEON）的增强，支持更高级的并行计算；安全异常级别（SEL），提供了硬件级别的安全性，允许操作系统在不同的安全级别上运行不同的任务；以及虚拟化支持，使得在一个物理系统上运行多个操作系统实例成为可能。 ARMv8指令集的引入不仅扩展了ARM处理器的能力，使其能够处理更复杂的计算任务，而且通过与现有32位系统的兼容性保持了软件生态的连续性。这一全面的指令集改进对于ARM架构在服务器、数据中心以及高端移动设备市场中的竞争力起到了关键作用。

ARMv8 Instruction Set Overview

PRD03-GENC-010197

2. Instructions which are truly conditionally executed (i.e. when the condition is false they have no effect on

the architectural state, aside from advancing the program counter) have the condition appended to the

instruction with a '.' delimiter. For example B.EQ.

3. If there is more than one instruction extension, then the conditional extension is always last.

4. Where a conditional instruction has qualifiers, the qualifiers follow the condition.

5. Instructions which are unconditionally executed, but use the condition flags as a source operand, will

specify the condition to test in their final operand position, e.g. CSEL Wd,Wm,Wn,NE

To aid portability an A64 assembler may also provide the old UAL conditional mnemonics, so long as they have

direct equivalents in the A64 ISA. However, the UAL mnemonics will not be generated by an A64 disassembler –

their use is deprecated in 64-bit assembler code, and may cause a warning or error if backward compatibility is

not explicitly requested by the programmer.

The full list of condition codes is as follows:

Encoding

Name

alias)

Meaning (integer) Meaning (floating point) Flags

0000 EQ

Equal Equal

Z==1

0001 NE

Not equal Not equal, or unordered

Z==0

0010

(CS)

Unsigned higher or same

(Carry set)

Greater than, equal, or unordered

C==1

0011

(CC)

Unsigned lower

(Carry clear)

Less than

C==0

0100 MI

Minus (negative) Less than

N==1

0101 PL

Plus (positive or zero) Greater than, equal, or unordered

N==0

0110 VS

Overflow set Unordered

V==1

0111 VC

Overflow clear Ordered

V==0

1000 HI

Unsigned higher Greater than, or unordered

C==1 && Z==0

1001 LS

Unsigned lower or same Less than or equal

!(C==1 && Z==0)

1010 GE

Signed greater than or

equal

Greater than or equal

N==V

1011 LT

Signed less than Less than or unordered

N!=V

1100 GT

Signed greater than Greater than

Z==0 && N==V

1101 LE

Signed less than or equal Less than, equal, or unordered

!(Z==0 && N==V)

1110 AL

1111 NV

†

Always Always

Any

†The condition code NV exists only to provide a valid disassembly of the ‘1111b’ encoding, and otherwise behaves

identically to AL.

ARMv8 Instruction Set Overview

PRD03-GENC-010197

4.4 Register Names

4.4.1 General purpose (integer) registers

The thirty one general purpose registers in the main integer register bank are named R0 to R30, with special

registers are used in a specific instruction form, they must be further qualified to indicate the operand data size (32

or 64 bits) – and hence the instruction’s data size.

The qualified names for the general purpose registers are as follows, where ‘n’ is the register number 0 to 30:

Size (bits)

32b 64b

Name

Wn Xn

Where register number 31 represents read zero or discard result (aka the “zero register”):

Size (bits)

32b 64b

Name

WZR XZR

Where register number 31 represents the stack pointer:

Size (bits)

32b 64b

Name

WSP

In more detail:

• The names Xn and Wn refer to the same architectural register.

• There is no register named W31 or X31.

• For instruction operands where register 31 in interpreted as the 64-bit stack pointer, it is represented by

the name SP. For operands which do not interpret register 31 as the 64-bit stack pointer this name shall

cause an assembler error.

• The name WSP represents register 31 as the stack pointer in a 32-bit context. It is provided only to allow a

valid disassembly, and should not be seen in correctly behaving 64-bit code.

• For instruction operands which interpret register 31 as the zero register, it is represented by the name XZR

in 64-bit contexts, and WZR in 32-bit contexts. In operand positions which do not interpret register 31 as

the zero register these names shall cause an assembler error.

• Where a mnemonic is overloaded (i.e. can generate different instruction encodings depending on the data

size), then an assembler shall determine the precise form of the instruction from the size of the first

some cases a register may have a different size (e.g. an address base register is always 64 bits), and a

source register may be smaller than the destination if it contains a word, halfword or byte that is being

widened by the instruction to 64 bits.

• The architecture does not define a special name for register 30 that reflects its special role as the link

Standard.

ARMv8 Instruction Set Overview

PRD03-GENC-010197

4.4.2 FP/SIMD registers

The thirty two registers in the FP/SIMD register bank named V0 to V31 are used to hold floating point

operands for the scalar floating point instructions, and both scalar and vector operands for the Advanced

SIMD instructions. As with the general purpose integer registers, when they are used in a specific instruction

form the names must be further qualified to indicate the data shape (i.e. the data element size and number of

elements or lanes) held within them.

Note however that the data type, i.e. the interpretation of the bits within each register or vector element –

integer (signed, unsigned or irrelevant), floating point, polynomial or cryptographic hash – is not described by

the register name, but by the instruction mnemonics which operate on them. For more details see the

Advanced SIMD description in §5.7.

4.4.2.1 SIMD scalar register

In Advanced SIMD and floating point instructions which operate on scalar data the FP/SIMD registers behave

similarly to the main general-purpose integer registers, i.e. only the lower bits are accessed, with the unused

high bits ignored on a read and set to zero on a write. The qualified names for scalar FP/SIMD names indicate

the number of significant bits as follows, where ‘n’ is a register number 0 to 31:

Size (bits)

8b 16b

32b 64b 128b

Name

Bn Hn Sn Dn Qn

4.4.2.2 SIMD vector register

When a register holds multiple data elements on which arithmetic will be performed in a parallel, SIMD

fashion, then a qualifier describes the vector shape: i.e. the element size, and the number of elements or

“lanes”. Where “bits



lanes” does not equal 128, the upper 64 bits of the register are ignored when read and

set to zero on a write.

The fully qualified SIMD vector register names are as follows, where ‘n’ is the register number 0 to 31:

Shape (bits



lanes)



8 8b



16 16b



16b



32b



32b



4 64b



1 64b



Name

Vn.8B Vn.16B Vn.4H Vn.8H Vn.2S Vn.4S Vn.1D Vn.2D

4.4.2.3 SIMD vector element

Where a single element from a SIMD vector register is used as a scalar operand, this is indicated by

appending a constant, zero-based “element index” to the vector register name, inside square brackets. The

number of lanes is not represented, since it is not encoded, and may only be inferred from the index value.

Size (bits)

8b 16b 32b 64b

Name

Vn.B[i] Vn.H[i] Vn.S[i] Vn.D[i]

However an assembler shall accept a fully qualified SIMD vector register name as in §4.4.2.2, so long as the

number of lanes is greater than the index value. For example the following forms will both be accepted by an

assembler as the name for the 32-bit element in bits <63:32> of SIMD register 9:

V9.S[1] standard disassembly

V9.2S[1] optional number of lanes

V9.4S[1] optional number of lanes

ARMv8 Instruction Set Overview

PRD03-GENC-010197

4.5 Load/Store Addressing Modes

Load/store addressing modes in the A64 instruction set broadly follows T32 consisting of a 64-bit base register

(Xn or SP) plus an immediate or register offset.

Type Immediate Offset

Simple register (exclusive)

[base{,#0}]

n/a n/a

Offset

[base{,#imm}] [base,Xm{,LSL #imm}] [base,Wm,(S|U)XTW {#imm}]

Pre-indexed

[base,#imm]!

n/a n/a

Post-indexed

[base],#imm

n/a n/a

PC-relative (literal) load

label

n/a n/a

• An immediate offset is encoded in various ways, depending on the type of load/store instruction:

Bits Sign Scaling Write-

back?

Load/Store Type

0 -

- - exclusive / acquire / release

7 signed

scaled option register pair

9 signed

unscaled option single register

12 unsigned

scaled no single register

• Where an immediate offset is scaled, it is encoded as a multiple of the data access size (except PC-

relative loads, where it is always a word multiple). The assembler always accepts a byte offset, which is

converted to the scaled offset for encoding, and a disassembler decodes the scaled offset encoding and

displays it as a byte offset. The range of byte offsets supported therefore varies according to the type of

load/store instruction and the data access size.

• The "post-indexed" forms mean that the memory address is the base register value, then base plus

offset is written back to the base register.

• The "pre-indexed" forms mean that the memory address is the base register value plus offset, then the

computed address is written back to the base register.

• A “register offset” means that the memory address is the base register value plus the value of 64-bit index

• An “extended register offset” means that the memory address is the base register value plus the value of

32-bit index register Wm, sign or zero extended to 64 bits, then optionally scaled by the access size.

• An assembler should accept Xm as an extended index register, though Wm is preferred.

• The pre/post-indexed forms are not available with a register offset.

• There is no "down" option, so subtraction from the base register requires a negative signed immediate

offset (two's complement) or a negative value in the index register.

• When the base register is SP the stack pointer is required to be quadword (16 byte, 128 bit) aligned prior

to the address calculation and write-backs – misalignment will cause a stack alignment fault. The stack

pointer may not be used as an index register.

• Use of the program counter (PC) as a base register is implicit in literal load instructions and not permitted

in other load or store instructions. Literal loads do not include byte and halfword forms. See section 5

below for the definition of label.

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