PIC16F684单片机全面解析：硬件资源与寄存器详情

需积分: 10 86 浏览量更新于2024-07-29 收藏 2.51MB PDF 举报

"PIC16F684 PIC单片机的规格书提供了关于这款14引脚闪存型8位CMOS微控制器的详细信息，包括其硬件资源和寄存器描述，是进行PIC单片机软件开发的重要参考资料。" PIC16F684是一款由Microchip Technology Inc.生产的微控制器，属于PIC16系列，采用nanoWatt技术，专为低功耗应用设计。该规格书详细介绍了以下关键知识点： 1. **硬件资源**：PIC16F684具有14个引脚，内部包含8位CPU、闪存程序存储器、RAM数据存储器以及一系列外围设备。这些外围设备可能包括定时器/计数器、串行通信接口（如UART）、模拟比较器、PWM（脉宽调制）模块等。 2. **闪存程序存储器**：这是PIC16F684存储用户程序的地方。闪存允许在不需外部编程设备的情况下进行多次编程和擦除，为开发过程提供了便利。 3. **寄存器**：规格书中详细列出了所有内部寄存器的功能和操作，这些寄存器用于控制和配置微控制器的各种功能。例如，配置寄存器用于设定系统时钟源、中断优先级、电源管理模式等；状态寄存器记录程序执行过程中的条件和状态。 4. **nanoWatt技术**：这项技术使PIC16F684在待机模式下能实现极低的功耗，适用于电池供电或能量采集等应用。 5. **器件应用**：虽然规格书中的信息是建议性的，但提供了如何将微控制器应用于不同场景的指导。用户应确保自己的应用满足具体需求，并对任何潜在的专利侵权负责。 6. **安全与合规**：Microchip声明其产品不授权用于生命支持系统的关键组件，除非获得公司书面批准。此外，规格书中的信息可能会更新，使用时需确保使用最新版本。 7. **商标与知识产权**：Microchip强调，其商标和知识产权不应被未经许可地使用，且不保证提供任何知识产权的许可。 PIC16F684规格书是开发者深入了解和使用该微控制器的必备文档，它涵盖了从硬件架构到软件开发所需的全部细节，对于理解和优化基于PIC16F684的系统设计至关重要。

PIC16F684

DS41202C-page 14 Preliminary  2004 Microchip Technology Inc.

2.2.2.4 PIE1 Register

The PIE1 register contains the interrupt enable bits, as

shown in Register 2-4.

Note: Bit PEIE (INTCON<6>) must be set to

enable any peripheral interrupt.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

EEIE ADIE CCP1IE C2IE C1IE OSFIE TMR2IE TMR1IE

bit 7 bit 0

bit 7 EEIE: EE Write Complete Interrupt Enable bit

1 = Enables the EE write complete interrupt

0 = Disables the EE write complete interrupt

bit 6 ADIE: A/D Converter Interrupt Enable bit

1 = Enables the A/D converter interrupt

0 = Disables the A/D converter interrupt

bit 5 CCP1IE: CCP1 Interrupt Enable bit

1 = Enables the CCP1 interrupt

0 = Disables the CCP1 interrupt

bit 4 C2IE: Comparator 2 Interrupt Enable bit

1 = Enables the Comparator 2 interrupt

0 = Disables the Comparator 2 interrupt

bit 3 C1IE: Comparator 1 Interrupt Enable bit

1 = Enables the Comparator 1 interrupt

0 = Disables the Comparator 1 interrupt

bit 2 OSFIE: Oscillator Fail Interrupt Enable bit

1 = Enables the oscillator fail interrupt

0 = Disables the oscillator fail interrupt

bit 1 TMR2IE: Timer2 to PR2 Match Interrupt Enable bit

1 = Enables the Timer2 to PR2 match interrupt

0 = Disables the Timer2 to PR2 match interrupt

bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit

1 = Enables the Timer1 overflow interrupt

0 = Disables the Timer1 overflow interrupt

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

 2004 Microchip Technology Inc. Preliminary DS41202C-page 15

PIC16F684

2.2.2.5 PIR1 Register

The PIR1 register contains the interrupt flag bits, as

shown in Register 2-5.

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>). User

software should ensure the appropriate

interrupt flag bits are clear prior to

enabling an interrupt.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

EEIF ADIF CCP1IF C2IF C1IF OSFIF TMR2IF TMR1IF

bit 7 bit 0

bit 7 EEIF: EEPROM Write Operation Interrupt Flag bit

1 = The write operation completed (must be cleared in software)

0 = The write operation has not completed or has not been started

bit 6 ADIF: A/D Interrupt Flag bit

1 = A/D conversion complete

0 = A/D conversion has not completed or has not been started

bit 5 CCP1IF: CCP1 Interrupt Flag bit

Capture mod

1 = A TMR1 register capture occurred (must be cleared in software)

0 = No TMR1 register capture occurred

Compare mode:

1 = A TMR1 register compare match occurred (must be cleared in software)

0 = No TMR1 register compare match occurred

PWM mode

Unused in this mode

bit 4 C2IF: Comparator 2 Interrupt Flag bit

1 = Comparator 2 output has changed (must be cleared in software)

0 = Comparator 2 output has not changed

bit 3 C1IF: Comparator 1 Interrupt Flag bit

1 = Comparator 1 output has changed (must be cleared in software)

0 = Comparator 1 output has not changed

bit 2 OSFIF: Oscillator Fail Interrupt Flag bit

1 = System oscillator failed, clock input has changed to INTOSC (must be cleared in software)

0 = System clock operating

bit 1 TMR2IF: Timer2 to PR2 Match Interrupt Flag bit

1 = Timer2 to PR2 match occurred (must be cleared in software)

0 = Timer2 to PR2 match has not occurred

bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit

1 = Timer1 register overflowed (must be cleared in software)

0 = Timer1 has not overflowed

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

 2004 Microchip Technology Inc. Preliminary DS41202C-page 17

PIC16F684

2.3 PCL and PCLATH

The Program Counter (PC) is 13 bits wide. The low byte

comes from the PCL register, which is a readable and

writable register. The high byte (PC<12:8>) is not

directly readable or writable and comes from PCLATH.

On any Reset, the PC is cleared. Figure 2-3 shows the

two situations for the loading of the PC. The upper

example in Figure 2-3 shows how the PC is loaded on a

write to PCL (PCLATH<4:0> → PCH). The lower exam-

ple in Figure 2-3 shows how the PC is loaded during a

CALL or GOTO instruction (PCLATH<4:3> → PCH).

FIGURE 2-3: LOADING OF PC IN

DIFFERENT SITUATIONS

2.3.1 COMPUTED GOTO

A computed GOTO is accomplished by adding an offset

to the program counter (ADDWF PCL). When perform-

ing a table read using a computed GOTO method, care

should be exercised if the table location crosses a PCL

memory boundary (each 256-byte block). Refer to the

Application Note AN556, “Implementing a Table Read”

(DS00556).

2.3.2 STACK

The PIC16F684 Family has an 8-level x 13-bit wide

hardware stack (see Figure 2-1). The stack space is

not part of either program or data space and the stack

pointer is not readable or writable. The PC is PUSHed

onto the stack when a CALL instruction is executed or

an interrupt causes a branch. The stack is POPed in

the event of a RETURN, RETLW or a RETFIE

instruction execution. PCLATH is not affected by a

PUSH or POP operation.

The stack operates as a circular buffer. This means that

after the stack has been PUSHed eight times, the ninth

push overwrites the value that was stored from the first

push. The tenth push overwrites the second push (and

so on).

2.4 Indirect Addressing, INDF and

FSR Registers

The INDF register is not a physical register. Addressing

the INDF register will cause indirect addressing.

Indirect addressing is possible by using the INDF

actually accesses data pointed to by the File Select

produce 00h. Writing to the INDF register indirectly

results in a no operation (although Status bits may be

affected). An effective 9-bit address is obtained by

concatenating the 8-bit FSR and the IRP bit

(Status<7>), as shown in Figure 2-4.

A simple program to clear RAM location 20h-2Fh using

indirect addressing is shown in Example 2-1.

EXAMPLE 2-1: INDIRECT ADDRESSING

12 8 7 0

PCLATH<4:0>

PCLATH

Instruction wit

ALU Result

GOTO, CALL

OPCODE <10:0

12 11 10 0

PCLATH<4:3>

PCH PCL

PCLATH

PCH PCL

PCL a

Destinatio

Note 1: There are no Status bits to indicate stack

overflow or stack underflow conditions.

2: There are no instructions/mnemonics

called PUSH or POP. These are actions

that occur from the execution of the

CALL, RETURN, RETLW and RETFIE

instructions or the vectoring to an

interrupt address.

MOVLW0x20;initialize pointer

MOVWFFSR ;to RAM

NEXT CLRFINDF ;clear INDF register

INCFFSR ;INC POINTER

BTFSSFSR,4;all done?

GOTONEXT ;no clear next

CONTINUE ;yes continue

剩余163页未读，继续阅读

shaoqianfei

粉丝: 0
资源: 3

PIC16F684单片机全面解析：硬件资源与寄存器详情

PIC12F1571规格书中文资料

PIC16F684 数据手册

PIC16F688中文数据手册

pic16f684单片机中文数据手册

PIC16F73/76单片机技术规格说明书

PIC16F690中文规格书

pic16f1937中文规格书

pic16f 单片机 英文使用说明

PIC16F18323/PIC16F18313数据手册（中文版）带书签

C641729-单片机(MCU-MPU-SOC)-PIC16F1938-E-SS-规格书-MICROCHIP(美国微芯)单片机(

最新资源

pic16f 单片机英文使用说明