e200z3嵌入式微处理器核心用户手册

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"e200z3RM.pdf 是一份用户手册，专注于介绍e200z3嵌入式微处理器核心的功能，旨在服务于软件和硬件开发人员。手册作为其他相关文档的补充，详细阐述了e200z3、e200z335核心的特性。" 本文档是Freescale Semiconductor（飞思卡尔半导体）于2008年6月发布的e200z3 Power Architecture™ Core Reference Manual，主要涵盖了e200z3系列微处理器的核心功能和技术细节。e200z3是一款基于Power Architecture技术的嵌入式处理器核心，具有高效能和低功耗的特点，适用于各种嵌入式系统设计。手册中可能包含了以下关键知识点： 1. **e200z3核心架构**：详细描述了e200z3核心的设计原理，包括其指令集体系结构（ISA）、处理单元、寄存器配置、内存管理单元（MMU）以及中断处理机制等。 2. **性能特征**：分析了e200z3在不同工作负载下的性能表现，如时钟速度、运算能力、能源效率等，帮助开发者评估其在目标应用中的适用性。 3. **硬件接口**：详述了e200z3与外围设备交互的接口标准，如HyperTransport、RapidIO等高速互连技术，以及对IEEE标准协议的支持，如IEEE nnn, nnn, nnn等。 4. **开发工具支持**：可能提到了针对e200z3的开发环境和工具链，如编译器、调试器、仿真器等，这些工具对于软件开发至关重要。 5. **知识产权保护**：文档指出，所有产品和服务名称属于各自所有者的财产，强调了知识产权的重要性，同时也声明该产品并未获得IEEE的官方认可。 6. **法律条款**：最后，手册中包含了一般性的法律声明，指出信息仅用于帮助系统和软件实施者使用Freescale Semiconductor的产品，不提供任何明示或暗示的版权许可。这份e200z3RM.pdf文档是开发者深入理解并有效利用e200z3微处理器核心进行系统和应用开发的重要参考资料。它提供了全面的技术细节和指导，有助于提高开发效率，确保产品的稳定性和性能。

e200z3 Power Architecture Core Reference Manual, Rev. 2

2 Freescale Semiconductor

Figures

Figure

Number Title

Page

Number

2-35 DBCR2 Register ................................................................................................................... 2-40

2-36 DBCR3 Register ................................................................................................................... 2-43

2-37 DBSR Register...................................................................................................................... 2-47

2-38 Hardware Implementation-Dependent Register 0 (HID0).................................................... 2-49

2-39 Hardware Implementation-Dependent Register 1 (HID1).................................................... 2-51

2-40 Branch Unit Control and Status Register (BUCSR) ............................................................. 2-52

2-41 MMU Control and Status Register 0 (MMUCSR0) ............................................................. 2-53

2-42 MMU Configuration Register 1 (MMUCFG) ...................................................................... 2-53

2-43 TLB Configuration Register 0 (TLB0CFG) ......................................................................... 2-54

2-44 TLB Configuration Register 1 (TLB1CFG) ......................................................................... 2-55

2-45 MAS Register 0 (MAS0) Format.......................................................................................... 2-56

2-46 MMU Assist Register 1 (MAS1) .......................................................................................... 2-56

2-47 MMU Assist Register 2 (MAS2) .......................................................................................... 2-57

2-48 MMU Assist Register 3 (MAS3) .......................................................................................... 2-58

2-49 MMU Assist Register 4 (MAS4) .......................................................................................... 2-59

2-50 MMU Assist Register 6 (MAS6))......................................................................................... 2-60

2-51 Process ID Register (PID0)................................................................................................... 2-60

2-52 Context Control Register (CTXCR) ..................................................................................... 2-61

2-53 Parallel Signature Control Register (PSCR) ......................................................................... 2-68

2-54 Parallel Signature Status Register (PSSR)............................................................................ 2-69

2-55 Parallel Signature High Register (PSHR) ............................................................................. 2-70

2-56 Parallel Signature Low Register (PSLR) .............................................................................. 2-70

2-57 Parallel Signature Counter Register (PSCTR)...................................................................... 2-70

2-58 Parallel Signature Update High Register (PSUHR).............................................................. 2-71

2-59 Parallel Signature Update Low Register (PSULR)............................................................... 2-71

4-1 Exception Syndrome Register (ESR)...................................................................................... 4-4

4-2 Machine State Register (MSR) ............................................................................................... 4-5

4-3 Machine Check Syndrome register (MCSR) .......................................................................... 4-7

4-4 Interrupt Vector Prefix Register (IVPR) ................................................................................. 4-8

4-5 Interrupt Vector Offset Registers (IVOR)............................................................................... 4-9

5-1 Effective-to-Real Address Translation Flow........................................................................... 5-3

5-2 Virtual Address and TLB-Entry Compare Process ................................................................. 5-5

5-3 Granting of Access Permission............................................................................................... 5-7

5-4 e200z3 TLB1 Organization.....................................................................................................5-8

5-5 Victim Selection...................................................................................................................... 5-9

5-6 MMU Assist Registers Summary ......................................................................................... 5-14

6-1 e200z3 Block Diagram............................................................................................................ 6-2

6-2 Pipeline Diagram..................................................................................................................... 6-4

6-3 Instruction Buffers ..................................................................................................................6-6

6-4 Branch Target Buffer............................................................................................................... 6-7

6-5 Basic Pipeline Flow, Single-Cycle Instructions...................................................................... 6-8

e200z3 Power Architecture Core Reference Manual, Rev. 2

Freescale Semiconductor 3

Figures

Figure

Number Title

Page

Number

6-6 A Load Followed by a Dependent Add Instruction ................................................................ 6-8

6-7 Back-to-Back Load Instructions ............................................................................................. 6-9

6-8 A Load Followed by a Dependent Store Instruction............................................................... 6-9

6-9 Basic Pipeline Flow, Branch Instructions ............................................................................. 6-10

6-10 Basic Pipeline Flow, Branch Speculation ............................................................................. 6-10

6-11 Basic Pipeline Flow, Multi-Cycle Instructions ..................................................................... 6-10

6-12 Pipelined Load/Store Instructions......................................................................................... 6-11

6-13 Pipelined Load/Store Instructions with Wait-State ............................................................... 6-11

6-14 mtspr, mfspr Instruction Execution—(1) .............................................................................. 6-12

6-15 mtmysr, wrtee, wrteei Instruction Execution...................................................................... 6-12

6-16 DCR, MMU mtspr, mfspr, and MMU Management Instruction Execution ....................... 6-13

6-17 Interrupt Recognition and Handler Instruction Execution.................................................... 6-14

6-18 Interrupt Recognition and Handler Instruction Execution—Load/Store in Progress ........... 6-15

6-19 Interrupt Recognition and Handler Instruction Execution—Multi-Cycle

Instruction Abort .............................................................................................................. 6-16

7-1 Core Signal Groups................................................................................................................. 7-3

7-2 Example External JTAG Register Design............................................................................. 7-28

7-3 Basic Read Transfer—Single-Cycle Reads, Full Pipelining................................................. 7-32

7-4 Read with Wait-State, Single-Cycle Reads, Full Pipelining.................................................7-33

7-5 Basic Write Transfers—Single-Cycle Writes, Full Pipelining.............................................. 7-34

7-6 Write with Wait-state, Single-Cycle Writes, Full Pipelining................................................ 7-35

7-7 Single-Cycle Reads, Single-Cycle Write, Full Pipelining .................................................... 7-36

7-8 Single-Cycle Read, Write, Read—Full Pipelining................................................................ 7-37

7-9 Multiple-Cycle Reads with Wait-State, Single-Cycle Writes, Full Pipelining ..................... 7-38

7-10 Multi-Cycle Read with Wait-State, Single-Cycle Write, Read with Wait-State, Single-Cycle

Write, Full Pipelining ....................................................................................................... 7-39

7-11 Misaligned Read, Read, Full Pipelining ............................................................................... 7-40

7-12 Misaligned Write, Write, Full Pipelining.............................................................................. 7-41

7-13 Misaligned Write, Single Cycle Read Transfer, Full Pipelining........................................... 7-42

7-14 Burst Read Transfer .............................................................................................................. 7-43

7-15 Burst Read with Wait-state Transfer ..................................................................................... 7-44

7-16 Burst Write Transfer..............................................................................................................7-45

7-17 Burst Write with Wait-State Transfer.................................................................................... 7-46

7-18 Burst Read Transfers............................................................................................................. 7-47

7-19 Burst Read with Wait-State Transfer, Retraction.................................................................. 7-48

7-20 Burst Write Transfers, Single-Beat burst .............................................................................. 7-49

7-21 Read Transfer with Wait-State, Address Retraction ............................................................. 7-50

7-22 Burst Read with Wait-State Transfer, Retraction.................................................................. 7-51

7-23 Read and Write Transfers: Instruction Read with Error, Data Read, Write,

Full Pipelining ..................................................................................................................7-52

7-24 Data Read with Error, Data Write Retracted, Instruction Read, Full Pipelining .................. 7-53

e200z3 Power Architecture Core Reference Manual, Rev. 2

4 Freescale Semiconductor

Figures

Figure

Number Title

Page

Number

7-25 Misaligned Write with Error, Data Write Retracted, Burst Read

Substituted, Full Pipelining.............................................................................................. 7-54

7-26 Burst Read with Error Termination, Burst Write .................................................................. 7-55

7-27 Read Transfer with Wait-State, Address Retraction ............................................................. 7-56

7-28 Burst Read with Wait-State Transfer, Retraction.................................................................. 7-57

7-29 Wakeup Control Signal (p_wakeup) ..................................................................................... 7-57

7-30 Interrupt Interface Input Signals ...........................................................................................7-58

7-31 Interrupt Pending Operation.................................................................................................. 7-58

7-32 Interrupt Acknowledge Operation Case 1............................................................................. 7-59

7-33 Interrupt Acknowledge Operation Case 2............................................................................. 7-60

8-1 Power Management State Diagram......................................................................................... 8-2

9-1 Core Debug Resources............................................................................................................ 9-3

9-2 OnCE TAP Controller and Registers .................................................................................... 9-11

9-3 OnCE Controller as an FSM................................................................................................. 9-12

9-4 OnCE Controller and Serial Interface................................................................................... 9-16

9-5 OnCE Status Register (OSR) ................................................................................................ 9-17

9-6 OnCE Command Register (OCMD)..................................................................................... 9-18

9-7 OnCE Control Register ......................................................................................................... 9-20

9-8 CPU Scan Chain Register (CPUSCR) .................................................................................. 9-25

9-9 Control State Register (CTL)................................................................................................ 9-26

9-10 OnCE PC FIFO ..................................................................................................................... 9-30

10-1 Nexus3 Functional Block Diagram....................................................................................... 10-4

10-2 Client Select Control Register............................................................................................. 10-10

10-3 Port Configuration Register ................................................................................................ 10-11

10-4 Development Control Register 1 (DC1) ............................................................................. 10-12

10-5 Development Control Register 2 (DC2) ............................................................................. 10-13

10-6 Development Status Register (DS) ..................................................................................... 10-14

10-7 Read/Write Access Control/Status Register (RWCS)......................................................... 10-15

10-8 Read/Write Access Data Register (RWD) .......................................................................... 10-16

10-9 Read/Write Access Address Register (RWA) ..................................................................... 10-17

10-10 Watchpoint Trigger Register (WT) ..................................................................................... 10-18

10-11 Data Trace Control Register (DTC).................................................................................... 10-19

10-12 Data Trace Start Address Registers 1 and 2 (DTSAn)........................................................ 10-20

10-13 Data Trace End Address Registers 1 and 2 (DTEAn)......................................................... 10-20

10-14 Nexus3 Register Access through JTAG/OnCE (Example)................................................. 10-21

10-15 Ownership Trace Message Format...................................................................................... 10-23

10-16 Error Message Format......................................................................................................... 10-23

10-17 Indirect Branch Message (History) Format ........................................................................ 10-26

10-18 Indirect Branch Message Format ........................................................................................ 10-26

10-19 Direct Branch Message Format........................................................................................... 10-26

10-20 Resource Full Message Format........................................................................................... 10-27

e200z3 Power Architecture Core Reference Manual, Rev. 2

Freescale Semiconductor 5

Figures

Figure

Number Title

Page

Number

10-21 Debug Status Message Format............................................................................................ 10-27

10-22 Program Correlation Message Format ................................................................................ 10-28

10-23 Error Message Format......................................................................................................... 10-29

10-24 Direct/Indirect Branch with Synchronization Message Format.......................................... 10-29

10-25 Indirect Branch History with Synchronization Message Format........................................ 10-30

10-26 Relative Address Generation and Re-Creation Example.................................................... 10-31

10-27 Program Trace—Indirect Branch Message (Traditional).................................................... 10-33

10-28 Program Trace—Indirect Branch Message (History) ......................................................... 10-33

10-29 Program Trace—Direct Branch (Traditional) and Error Messages .................................... 10-33

10-30 Program Trace—Indirect Branch with Synchronization Message...................................... 10-34

10-31 Data Write Message Format................................................................................................ 10-35

10-32 Data Read Message Format ................................................................................................ 10-35

10-33 Error Message Format......................................................................................................... 10-36

10-34 Data Write/Read with Synchronization Message Format...................................................10-36

10-35 Data Trace—Data Write Message....................................................................................... 10-39

10-36 Data Trace—Data Read with Synchronization Message.................................................... 10-39

10-37 Error Message (Data Trace Only Encoded) ........................................................................ 10-39

10-38 Watchpoint Message Format............................................................................................... 10-40

10-39 Error Message Format......................................................................................................... 10-41

10-40 Watchpoint Message and Watchpoint Error Message.........................................................10-41

10-41 Error Message Format......................................................................................................... 10-46

10-42 Single-Pin MSEO Transfers................................................................................................ 10-49

10-43 Dual-Pin MSEO Transfers.................................................................................................. 10-50

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