TI TPS65219：ARM Cortex-A53处理器与FPGA集成电源管理IC特性与应用

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TI-TPS65219是一款集成的电源管理集成电路，专为ARM Cortex-A53处理器和FPGA设计，旨在提供高效能、低功耗解决方案。该器件集成了多种功能，使其在多个应用领域中表现出色。核心特点包括： 1. **三种非固定频率（最高可达2.3MHz）的降压转换器**： - 一个输入电压范围为2.5V-5.5V，输出电流高达3.5A，输出电压可调至0.6V-3.4V。 - 另两个输入电压也为2.5V-5.5V，但输出电流降低到2A，输出电压同样支持0.6V-3.4V。 2. **四个线性稳压器**： - 有两个稳压器，输入电压范围1.5V-5.5V，最大输出电流400mA，可用于支持SD卡，电压可调至0.6V-3.4V，同时具备负载开关和旁路模式。 - 另外两个稳压器输入电压为2.2V-5.5V，输出电流300mA，输出电压1.2V-3.3V，同样可以作为负载开关使用。 3. **动态电压调整**：所有三路降压转换器支持动态电压调整，以适应不同的负载条件。 4. **低功耗工作模式**：支持低IQ/PFM和PWM工作模式，其中PWM工作频率可根据需求进行微调。 5. **可编程电源序列控制和默认电压设置**：便于系统设计者优化电源管理策略。 6. **集成I2C接口**：支持标准、快速模式和快速模式+，方便与外部设备通信。 7. **广泛的应用兼容性**：适用于低功耗工业MPU，如AM62x和AM64x系列，以及HMI、PLC、工业PC、建筑安全、HVAC、视频监控、数据集中器、智能电表和保护继电器等多样化的工业和消费电子应用。 8. **GPIO和多功能引脚**：提供了2个GPIO和3个多功能引脚，增强灵活性和扩展能力。 9. **可编程EEPROM**：支持通过EEPROM进行固件升级和配置，简化系统设计。 TI-TPS65219凭借其高效能、多电压输出选项、灵活的电源管理功能和广泛的适用性，是现代电子设备中理想的电源管理解决方案，尤其适合对功耗敏感的嵌入式系统和工业自动化应用。

7.3.2 Power-Down Sequencing

An OFF-request or a shut-down-fault will trigger the power-down sequence. The OFF-request may be triggered

by a falling edge on EN/PB/VSENSE if configured for EN or VSENSE respectively a long press of the push-

button if configured as PB or by an I2C-command to I2C_OFF_REQ in MFP_CTRL register. This bit self-clears.

An I2C-triggered shut-down will require a renewed ON-request on the EN/PB/VSENSE pin. In case of

EN- or VSENSE-configuration, a low-going edge followed by a high-going-edge is requiered on the EN/PB/

VSENSE-pin. The falling-edge deglitch time for EN or VSENSE configuration t

DEGL_EN/VSENSE_I2C

is shorter

than the deglitch-time for pin-induced OFF-requests (t

DEGL_EN_Fall

and t

DEGL_VSENSE_Fall

). The deglitch-times for

PB-configuration remain.

In many cases, the power-down sequence follows the reverse power-up sequence. In some applications, all

rails may be required to shut down at the same time with no delay between rails or require wait-times to allow

discharging of rail.

The power-down sequence is configured as follows:

• The slot (respectively the position in the sequence) for each rail and GPO1, GPO2, GPIO, and nRSTOUT is

defined using the xyz_SEQUENCE_SLOT registers, the four MSB for the ON-sequence, the four LSB for the

down-sequencing.

• The duration of each slot is defined in the POWER_DOWN_SLOT_DURATION_x registers and can be

configured as 0 ms, 1.5 ms, 3 ms or 10ms. In total, 16 slots can be configured, allowing the sequence to span

over multiple TPS65219-devices if more rails need to be supported.

• In addition to the slot-duration, the power-down sequence is also gated by the previous rail being discharged

below the SCG-threshold, unless active discharge is disabled on the previous rail. If that does not occur, the

power-down of subsequent rails is paused. To allow for power-down in case of biased or shorted rails, the

sequence continues despite an incomplete discharge of the previous rail after eight times the slot-duration (or

12 ms in case of slot-duartion of 0 ms).

• If this discharge-check shall be bypassed, the bit BYPASS_RAILS_DISCHARGED_CHECK in register

GENERAL_CONFIG can be set to '1'.

Note

In case active discharge on a rail is disabled, it will not gate the disable of the subsequent rail, but the

sequence will be purely timing based. In case of residual voltage, the RV-bit is be set regardless.

Active discharge is enabled by default and not NVM based. Thus, if desired, it need to be disabled after each

VSYS-power-cycle. During RESET or OFF-request, the discharge configuration is not reset, as long as VSYS

is present. However, in INITIALIZE state and prior to the power-up-sequence, all rails will get discharged,

regardless of the setting.

During the power-down-sequence, non-EEPROM-backed bits get reset, with the exception of unmasked

interrupt bits and *_DISCHARGE_EN bits.

Below graphic shows an example for a power-down-sequence.

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– In case of a cold reset (regardless if by RESET-pin or I2C-request), no renewed on-request is required,

i.e. the device will power-up again if EN input is still above the V

-threshold. (EN considered level-

sensitive)

• Push-Button (PB):

– The PB pin is a CMOS-type input used to power-up the PMIC. Typically, the PB pin is connected to a

momentary switch to ground and an external pullup resistor.

– The hold-time of the push-button is configured by EN_PB_VSENSE_DEGL in MFP_2_CONFIG register.

– The power-up sequence starts if the PB input is below the V

-threshold low for the configured t

PB_ON

– To signify the power-up based on an EN/PB/VSENSE pin-event, the device sets bit

POWER_UP_FROM_EN_PB_VSENSE in POWER_UP_STATUS_REG register.This bit will not assert the

nINT pin. Write W1C to clear the bit.

– The PB pin has a rising-edge deglitch t

PB_RISE

to filter bouncing of the switch

– The power-down sequence starts if the PB input is held low for t

PB_OFF

-time (not configurable).

– In case of a shut-down fault, no renewed on-request is required, i.e. the device will power-up again without

a PB-press.

– In case of a cold reset (regardless if by RESET-pin or I2C-request), no renewed on-request is required,

i.e. the device will power-up again without a PB-press.

– A push-button press is only recognized after VSYS is above VSYS_POR-threshold or must be held long

enough after VSYS is above VSYS_POR-threshold.

– Following bits in the signify the PB-press events:

• PB_FALLING_EDGE_DETECTED: PB was pressed for > deglitch period (64-218ms) since the

previous time this bit was cleared. This bit when set, will assert nINT pin (if config bit

MASK_INT_FOR_PB='0'). Write W1C to clear.

• PB_RISING_EDGE_DETECTED: PB was released for > deglitch period (64-218ms) since the previous

time this bit was cleared. This bit when set, will assert nINT pin (if config bit MASK_INT_FOR_PB='0').

Write W1C to clear.

• PB_REAL_TIME_STATUS: Deglitched (64-128ms) real-time status of PB pin. Valid only when EN/PB/

VSENSE pin is configured as PB. This bit will not assert the nINT pin.

• Power-fail comparator input (VSENSE):

– Connected to a resistor divider from the supply-line of the pre-regulator, this pin can be used to sense the

supply-voltage to the pre-regulator.

– The deglitch-time of the VSENSE-pin is configurable by EN_PB_VSENSE_DEGL in MFP_2_CONFIG

– Power-up is gated by VSYS being above the VSYS

POR_Rising

-threshold and the VSENSE input is above

the V

VSENSE

-threshold (not deglitched)

– The power-up sequence starts if the VSENSE input rises above V

VSENSE

– To signify the power-up based on an EN/PB/VSENSE pin-event, the device sets bit

POWER_UP_FROM_EN_PB_VSENSE in POWER_UP_STATUS_REG register. This bit will not assert

the nINT pin. Write W1C to clear the bit.

– The power-down sequence starts if the VSENSE input falls below the V

VSENSE

-threshold for

DEGL_VSENSE_Fall

, to avoid an un-sequenced power-off due to the loss of VSYS-supply-voltage.

– In case of a shut-down fault, no renewed on-request is required, i.e. the device will power-up again if

VSENSE input is still above the V

VSENSE

-threshold.

– In case of a cold reset (regardless if by RESET-pin or I2C-request), no renewed on-request is required,

i.e. the device will power-up again if VSENSE input is still above the V

VSENSE

-threshold.

• OFF-request by I2C-command

– An OFF-request can also be triggered by an I2C-command to I2C_OFF_REQ in MFP_CTRL register.

– After such an OFF-request, a new ON-request is required:

• In case of EN-configuration, the EN input requires a rising edge (EN considered edge-sensitive)

• In case of PB-configuration, the PB needs to be pressed for a valid ON-request

• In case of VSENSE-configuration, the VSENSE input requires a rising edge (VSENSE considered

edge-sensitive), i.e. a power-cycle on the supply to the pre-regulator will be required.

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• The falling-edge deglitch time for EN or VSENSE configuration t

DEGL_EN/VSENSE_I2C

is shorter than the

deglitch-time for pin-induced OFF-requests (t

DEGL_EN_Fall

and t

DEGL_VSENSE_Fall

). The deglitch-times for

PB-configuration remain.

• First Supply detection (FSD)

– First Supply detection (FSD) allows power-up as soon as supply voltage is applied, even if EN/PB/

VSENSE pin is at OFF_REQ status.

– FSD can be used in combination with any ON-request configuration, EN, PB or VSENSE.

– FSD can be enabled by setting PU_ON_FSD bit in MFP_2_CONFIG.

– At first power-up the EN/PB/VSENSE pin is treated as if it had a valid ON request.

– Once VSYS is above the VSYS

POR_Rising

-threshold, the PMIC

• loads the EEPROM

• enters INITIALIZE state

• perform the discharge-check

• initiates the power-up-sequence, regardless of the EN/PB/VSENSE-pin-state.

– To signify the power-up based on FSD, the device sets bit POWER_UP_FROM_FSD in

POWER_UP_STATUS_REG register. The nINT-pin will not toggle based on this bit. Write W1C to clear

the bit.

– Thereafter, the EN/PB/VSENSE-pin is treated as if it had a valid ON-request, until we enter ACTIVE state

(at the expiration of the last slot in the power-up-sequence).

– After that the device adheres to post-deglitch EN/PB/VSENSE-pin-status: if pin status has changed prior

to entering ACTIVE state or in ACTIVE state, the device will adhere to it. E.g. if the EN/PB/VSENSE-pin is

configured for EN, the device will power down in case the EN-pin is low (for longer than the deglitch time)

at the time the device enters ACTIVE state.

– The duration for how long the ON-request is considered valid, regardless of the pin-state, can be

controlled by length of nRSTOUT slot (and empty slots thereafter), as the PMIC enters ACTIVE state

only after the last slot of the sequence expired.

7.3.4 Reset to SoC (nRSTOUT)

The reset output (nRSTOUT) is an open-drain output, intended to release the reset to the SoC or FPGA at the

end of the power-up sequence. The timing for nRSTOUT is configured in the sequence. nRSTOUT is driven low

until the device enters ACTIVE state or when powering-down from ACTIVE- or STBY-state. The pin is driven

high during ACTIVE- and STBY-state.

7.3.5 Buck Converters (Buck1, Buck2, and Buck3)

The TPS65219 provides three buck converters, Buck1 capable of providing up to 3.5 A load current, Buck2 and

Buck3 capable of 2 A load current each. The buck converters have an input voltage range from 2.5 V to 5.5 V,

and can be connected either directly to the system power or the output of a another buck converter. The output

voltage is programmable in the range of 0.6 V to 3.4 V: in 25mV-steps up to 1.4V, in 100mV-steps between 1.4V

and 3.4V.

• The ON/OFF state of the buck converters in ACTIVE state is controlled by the corresponding BUCKx_EN bit

in the ENABLE_CTRL register.

• The ON/OFF state of the buck converters in STBY state is controlled by the corresponding

BUCKx_STBY_EN bit in the STBY_1_CONFIG register.

• In INITIALIZE state, the buck converters are off, regardless of bit-settings.

CAUTION

Also, buck-regulators that are unused or shall not be enabled during the power-up-sequence must

still be configured for output voltage and sequencing-slot.

The respective BUCKx_EN-bit is set low to avoid powering-up. In case of rails that are not used at

all, the FB_Bx pin shall be tied to GND and the LX_Bx pin(s) shall be left floating.

• The converters activity can be controlled by the sequencer or through I2C communication.

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• The TPS65219 offers a variety of switch-modes:

• in quasi-fixed-frequency mode, the converters can operate in forced-PWM mode, irrespective of load-current,

or can be allowed to enter pulse-frequency-modulation (PFM) for low load-currents. The mode is contolled

by either the MODE/STBY pin or the MODE/RESET pin if either of those is configured as 'MODE', or by an

I2C-command to MODE_I2C_CTRL bit in MFP_1_CONFIG register (see pin-configuration and I2C-command

in 'PWM/PFM and Low Power Modes (MODE/STBY)' and PWM/PFM and Reset (MODE/RESET)' section.

– During a transition to ACTIVE state or to INITIALIZE state, the buck converters are forced to PWM,

irrespective of the pin-state. PFM-entry is only allowed when the device enters ACTIVE state, i.e. upon

completion of the sequence and expiration of the last power-up-slot.

– In case of a DVFS-induced output voltage change, the TPS65219 will temporarily force the buck-

regulators into PWM until the voltage change completed.

– During an I2C-induced power-up of any one of the three bucks, a MODE-change is blanked and will only

take effect after the ramp completed.

– If PFM is allowed, the entry and exit into PFM is load-current dependent. PFM starts when the inductor

current reaches 0 A, which is the case at a load current appoximately calculated by:

– I

LOAD

= {[(V

PVIN_Bx

- V

BUCKx

) / L] × (V

BUCKx

/ V

PVIN_Bx

) × (1 / f

)} / 2

• The converters can be individually configured further for a high-bandwidth-mode for optimum transient-

response or lower bandwidth, allowing minimum output filter capacitance. The selection is done by the

BUCKx_BW_SEL bits in GENERAL_CONFIG register . This bit must only change if this regulator is disabled.

Please note the higher output-capacitance requirements for high bandwidth use case!

• If VSEL_SD/VSEL_DRR is configured as 'VSEL_DDR' by the VSEL_DDR_SD bit in MFP_1_CONFIG

leave it floating. These settings supports DDR3LV, DDR4, and DDR4LV supply voltages without an EEPROM

change.

CAUTION

The VSEL_DDR-pin shall be hardwired and must not change voltage while the PMIC is enabled.

• The buck converters have an active discharge function. The discharge function can be disabled individually

per rail in the DISCHARGE_CONFIG register. If discharge is enabled, the device discharges the output is

discharged to ground whenever a rail is disabled.

• Prior to a sequence into ACTIVE state (from INITIALIZE or STBY state), the device discharges the disabled

rails regardless of the discharge-configuration to avoid starting into a pre-biased output.

• If a rail is enabled by an I2C-command, active discharge is not enforced, but the rail is only enabled if the

output voltage is below the SCG-threshold.

• This register is not EEPROM-backed and will reset if the device enters OFF-state.

• When in INITIALIZE state (during RESET or an I2C-OFF-request), the discharge configuration is not reset.

Note: the power-down-sequence may be violated if the discharge function is disabled.

All Buck Converters support Dynamic Voltage Frequency Scaling (DVFS). The output-voltage can be changed

during the operation to optimize the operating voltage for the operation point of the SoC in the lower output

voltage range between 0.6 V and 1.4 V. The voltage change is controlled by writing to BUCK1_VOUT

respectively BUCK2_VOUT or BUCK3_VOUT registers. During a DVFS-induced voltage transition, the active

discharge function is temporarily enabled, irrespective of the discharge-configuration.

Output Capacitance Requirements

The buck converters require sufficient output-capacitance for stability. The required minimum and supported

maximum capacitance depends on the configuration:

• for quasi-fixed-frequency, low-bandwidth configuration, a minimum capacitance of 10uF is required and a

maximum total capacitance of 75uF is supported

• for quasi-fixed-frequency, high-bandwidth configuration, a minimum capacitance of 30uF is required and a

maximum total capacitance of 220uF is supported

Buck Fault Handling

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