PCB设计指南：降低电磁干扰(EMI)
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本资源是TI公司的一份应用笔记，专注于PCB设计中的关键原则、方法和注意事项，旨在帮助设计者实现更好的电磁兼容性(EMI)性能。这份文档虽然有些年份，但仍然具有很高的参考价值。文档通过一系列插图和说明，详细探讨了以下几个方面：
1. **信号频率的影响**：图1指出，低于50kHz的信号不构成EMI问题。这表明在设计时，高频信号的管理对于减少EMI至关重要。
2. **环路与噪声**：图2展示了不同类型的环路，并解释了它们如何产生噪声。理解这些环路是减小EMI的关键，因为它们可能导致不必要的辐射。
3. **差分模式与共模噪声**：图3比较了两者之间的差异，强调了控制噪声传播方式对降低EMI的重要性。
4. **微计算机地线设计**：图4讨论了地线布局对EMI的影响，强调了良好的接地设计对于系统稳定性的作用。
5. **布局考虑**：图5提到了在设计过程中应考虑的因素，如元件布局、走线长度和方向，这些都会影响EMI的水平。
6. **电源分布**：图6探讨了电源分配策略，指出均匀且有效的电源分配有助于减少噪声。
7. **双层板电源迹线格栅化**：图7和8说明了如何通过格栅化电源和地线来创建一个地平面，从而减少EMI。
8. **铁氧体珠的放置**：图9建议将铁氧体珠靠近噪声源放置，以有效抑制噪声。
9. **区域划分**：图10介绍了板区划的概念，这是一种组织电路板上不同功能区域的方法，有助于EMI管理。
10. **MOS缓冲器简化原理图**：图11展示了MOS缓冲器的工作原理，说明了如何设计低EMI的驱动电路。
11. **前面板格栅化形成双地平面**：图12提供了如何在前面板设计中创建两个地平面以优化EMI性能的示例。
12. **外部I/O滤波电容安装**：图13给出了安装滤波电容的最佳实践，以过滤来自外部输入/输出的噪声。
这份笔记还强调了TI对产品的质量保证，以及使用半导体产品时可能涉及的安全风险和责任问题。它提醒设计者在订购前确认最新的产品信息，以确保信息的准确性和完整性。
这份资源为PCB设计者提供了一套实用的EMI降低策略，涵盖了从信号频率到组件布局的多个层面，是电子设计工程师不可或缺的参考资料。
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ABSTRACT
General layout guidelines for printed circuit boards (PCB), which exist in relatively obscure documents, are summarized. Some
guidelines apply specifically to microcontrollers; however, the guidelines are intended to be general, and apply to virtually all
modern CMOS integrated circuits. This document covers most known and published layout techniques as applied in a
low-noise, unshielded environment. Efforts have been made to target two-layer boards, and the maximum acceptable noise
level is assumed to be 30 dB, or greater, more stringent than FCC Part 15. This level seems to be the upper limit of acceptable
noise in European and U.S. automotive markets.
This document does not always explain the why’s of a given technique because it is intended only as a reference document,
not a teaching aid. The reader is cautioned against making the assumption that although on a prior design a given technique
was not applied and the unit had acceptable performance, that the technique is not useful. Over time, as IC devices increase
in speed and density, every method to isolate and reduce noise will be required.
1 Background
1.1 RF Sources
Design guidelines to be discussed concern radio-frequency (RF) noise from the microcomputer. This noise is generated inside
the device and is coupled out in many different possible ways. The noise is present on all outputs, inputs, power supply, and
ground at all times. Potentially, every pin on the microcomputer can be a problem.
The biggest problem is noise from the integrated-circuit (IC) input/output (I/O) pins. Because the area covered by traces
connected to them on the PCB form a large antenna. These pins also connect to both internal and external cables. The noise
from clock switching within the IC appears as ‘‘glitches” on a static output. The glitch is caused by the common impedance
of the output pin and the clock drivers, that is, the shared pins that supply each power and ground. The synchronous nature of
most devices causes all current-switching events to occur at the same time, making a large noise spike containing RF energy.
The second most-important contributor is the power-supply system, which includes the voltage regulation and the bypassing
capacitors at both the regulator and at the microcomputer. These circuits are the source of all the RF energy in the system, as
they feed the clocked circuits inside the IC with the current required for switching.
The third noise source is the oscillator circuit, where the oscillator swings rail to rail. In addition to the fundamental frequency,
harmonics are introduced on the output side because the output buffer is digital, which squares the sine wave. Also, any noise
caused by internal operations, such as the clock buffers, appears on the output. If proper separation is maintained between the
crystal and its tank circuits from other components and traces on the PCB, and the loop areas are kept small, there should be
no problems with this noise source. But it has been shown that if ICs or passive components, such as the main V
Batt
series
inductor, are placed close to the crystal, harmonics of the crystal can couple and propagate.
The primary focus in this application report is on the first and second previously described noise sources. The way to deal with
the third noise source has been addressed. Also, critical information is disclosed on board zoning (floor planning) and shielding.
1.2 Surface-Mount Devices vs Through-Hole Components
Surface-mount devices (SMD) are better than leaded devices in dealing with RF energy because of the reduced inductances
and closer component placements available. The latter is possible due to the reduced physical dimensions of SMDs. This is
critical to two-layer board design, where maximum effectiveness from noise-control components is needed. Generally, leaded
capacitors all go self-resonant (become more inductive than capacitive) at about 80 MHz. Because noise above 80 MHz needs
to be controlled, serious questions should be asked if a design is to be executed only with through-hole components.
1.3 Static Pins vs Active Pins vs Inputs
As mentioned previously, all lines have noise from the processor, to some degree. The total noise from a pin depends on how
much noise the microcomputer provides it and its function in the system. For example, an output pin has the noise from the
microcomputer’s power rails and the noise capacitively coupled from adjacent pins and the substrate. If the pin’s function is
the system clock, that too is noise. Even if the pin were static at a one or zero level, one would still have to contend with noise
from inside the chip.
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