The OS or application must ensure correct type of service and interrupt priority is configured in the SR
register. Enabling and disabling of interrupts must also be managed by the OS or application.
The OS files provided by the MCAL package is only an example code and must be updated by the integrator
with the actual OS files for the desired function.
1.1.4.2 Multicore and Resource Manager
The PWM driver supports execution of its APIs simultaneously from all CPU cores. The user should allocate
logical PWM channels to the CPU cores at pre-compile time using the Resource manager module. The following
are the key points to be considered with respect to multicore in the driver:
• Logical PWM channels are allocated to CPU cores at pre-compile time. For example, Pwm_Channel0,
Pwm_Channel1
• It must be ensured that PWM channel id passed as parameter while invoking an API belongs to the same
core
• DETs are raised in case APIs are invoked with mismatch of core and channel id
• Interrupts raised by a PWM channel must be serviced by the CPU core to which the channel has been
allocated to
• PWM channels using GTM-ATOM, channel GTM-ATOM[i]_CH[X] and ATOM[i]_CH[x+1] must be allocated to
the same core as these two channels share the same interrupt line
• PWM channels using GTM-TOM, channel GTM-TOM[i]_CH[X] and TOM[i]_CH[x+1] must be allocated to the
same core as these two channels share the same interrupt line
• Locating constants, variables and configuration data to the correct memory space should be done by the
user. Memory sections are marked GLOBAL (common to all cores) and CORE[x](specific to a CPU core). The
following should be considered by the user to ensure better performance of the driver:
Code section:
The executable code of the PWM driver is placed under single MemMap section. It can be relocated to any
PFlash.
Data section:
The RAM variable memory sections marked as specific to core should be relocated to the DSPR/DLMU of
the same core. The sections marked as global should be relocated to the non-cached LMU region.
Configuration data and constants:
The configuration data section sections marked as specific to core should be relocated to the PFlash of the
same core. The sections marked as global should be relocated to the PFlash of the master core.
Note: Relocating code, data and constants to a distant memory space would impact execution timings.
Note: If the driver operates from single (master) core, all the sections may be relocated to the PFlash/DSPR/
DLMU of the same CPU core.
1.1.4.3 MCU support
The PWM driver is dependent on the MCU driver for clock configuration, GTM timer to port pin connections and
timer IP-related services. The initialization of the PWM driver must be started only aer completing the MCU
initialization. The following must be considered while configuring the MCU driver in tresos:
• The GTM/CCU6 hardware timers used by the PWM driver must be reserved in the MCU configuration for
exclusive use by the PWM
• For signal output, the GTM timer to port pin connections should be configured in the MCU configuration for
each TOM/ATOM channel allocated for PWM
Access of shared GTM SFRs
restricted
MCAL User Manual for Pwm_17_GtmCcu6
32-bit TriCore
TM
AURIX
TM
TC3xx microcontroller
1 Pwm_17_GtmCcu6 driver
User Manual 17 Version 7.0
2022-07-05