TI SN65LV1023A-EP：10:1 LVDS 串行器/解串器技术规格
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"TI-SN65LV1023A-EP.pdf 是TI公司的一款LVDS（Low Voltage Differential Signaling）串行器，适用于10-MHz至66-MHz频率范围，可实现100-Mbps到660-Mbps的串行LVDS数据传输带宽。该器件是DS92LV1023/DS92LV1224的引脚兼容增强版本，具备扩展温度性能，可在-55°C至125°C的范围内稳定工作，并且功耗低，典型值在66MHz时小于450mW。"
详细说明：
TI的SN65LV1023A-EP是一款高性能的LVDS串行器，设计用于高速数字信号传输。LVDS技术是一种低电压差分信号标准，它以相对较低的电压差（通常在几百毫伏范围内）传输高速数据，具有低噪声、低功耗和高抗干扰能力的特性。
该器件的主要特点包括：
1. **数据传输速率**：SN65LV1023A-EP支持从10-MHz到66-MHz的系统时钟频率，对应的数据传输速率可达到100-Mbps至660-Mbps，适合高速数据传输应用。
2. **控制基线系统时钟**：设备采用控制基线系统时钟，确保了时钟的一致性和稳定性，有助于减少信号失真和提高系统性能。
3. **引脚兼容性**：与DS92LV1023/DS92LV1224引脚兼容，方便用户在现有设计中升级或替换，无需修改电路板布局。
4. **扩展温度范围**：在-55°C至125°C的温度范围内，该器件仍能保持可靠的工作性能，满足极端环境下的应用需求。
5. **低功耗**：在66MHz工作频率下，典型功耗仅为450mW，降低了系统的能耗。
6. **减小制造来源（DMS）支持**：支持增强的减小制造来源模式，提高了生产效率和一致性。
7. **锁合指示器**：内置锁合指示器，可以快速检测系统是否已锁定在正确的时钟频率上。
8. **产品变更通知增强**：提供更及时的产品变更通知，帮助客户及时了解产品更新情况。
9. **无外部PLL组件**：不需要外部组件来构建锁相环，简化了设计并减少了外部元件的成本。
10. **编程边沿触发时钟**：用户可以根据需要编程设置时钟的上升沿或下降沿触发，增加了设计的灵活性。
11. **封装选项**：提供28-Pin SSOP和节省空间的5x5mm QFNP封装，适应不同的应用场景。
这款器件在设计时考虑了可靠性和耐用性，按照JEDEC和行业标准进行了全面的资格认证，包括高度加速应力测试（HAST）、温度循环、高压蒸汽灭菌（autoclave）或无偏HAST等，以确保在扩展温度范围内的可靠操作。
SN65LV1023A-EP是适用于高速、低功耗、高可靠性应用的理想选择，特别适合于需要在严苛环境中运行的串行数据传输系统。
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POWER DOWN
HIGH-IMPEDANCE MODE
FAILSAFE BIASING FOR THE SN65LV1224B
SN65LV1023A-EP
SN65LV1224B-EP
SGLS358 – SEPTEMBER 2006
FUNCTIONAL DESCRIPTION (continued)
Once the deserializer has synchronized to the serializer, the LOCK pin transitions low. The deserializer locks to
the embedded clock and uses it to recover the serialized data. ROUT data is valid when LOCK is low, otherwise
R
OUT0
–R
OUT9
is invalid. The R
OUT0
–R
OUT9
data is strobed out by RCLK. The specific RCLK edge polarity to be
used is selected by the RCLK_R/F input. The R
OUT0
–R
OUT9
, LOCK and RCLK outputs can drive a maximum of
three CMOS input gates (15-pF load total for all three) with a 66-MHz clock.
When no data transfer is required, the power-down mode can be used. The serializer and deserializer use the
power-down state, a low-power sleep mode, to reduce power consumption. The deserializer enters power down
when you drive PWRDN and REN low. The serializer enters power down when you drive PWRDN low. In power
down, the PLL stops and the outputs enter a high-impedance state, which disables load current and reduces
supply current to the milliampere range. To exit power down, you must drive the PWRDN pin high.
Before valid data exchanges between the serializer and deserializer can resume, you must reinitialize and
resynchronize the devices to each other. Initialization of the serializer takes 1026 TCLK cycles. The deserializer
initialize and drives LOCK high until lock to the LVDS clock occurs.
The serializer enters the high-impedance mode when the DEN pin is driven low. This puts both driver output
pins (DO+ and DO–) into a high-impedance state. When you drive DEN high, the serializer returns to the
previous state, as long as all other control pins remain static (SYNC1, SYNC2, PWRDN, TCLK_R/ F). When the
REN pin is driven low, the deserializer enters high-impedance mode. Consequently, the receiver output pins
R
OUT0
–R
OUT9
) and RCLK are placed into the high-impedance state. The LOCK output remains active, reflecting
the state of the PLL.
Deserializer Truth Table
INPUTS OUTPUTS
PWRDN REN ROUT(0:9)
(1)
LOCK
(2)
RCLK
(1) (3)
H H Z H Z
H H Active L Active
L X Z Z Z
H L Z Active Z
(1) ROUT and RCLK are 3-stated when LOCK is asserted high.
(2) LOCK output reflects the state of the deserializer with regard to the selected data stream.
(3) RCLK active indicates the RCLK is running if the deserializer is locked. The timing of RCLK with respect to ROUT is determined by
RCLK_R/ F.
The SN65LV1224B has an input threshold sensitivity of ± 50 mV. This allows for greater differential noise margin
in the SN65LV1224B. However, in cases where the receiver input is not being actively driven, the increased
sensitivity of the SN65LV1224B can pickup noise as a signal and cause unintentional locking. This may occur
when the input cable is disconnected. The SN65LV1224B has an on-chip fail-safe circuit that drives the serial
input and LOCK signal high. The response time of the fail-safe circuit depends on interconnect characteristics.
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