PurePath Digital TAS5086: 六通道数字音频PWM处理器

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"TI-TAS5086.pdf是德州仪器（TI）生产的一款六通道纯路径数字音频PWM处理器的详细资料。" TI的TAS5086是一款高性能的音频处理芯片，专为提供高质量的多声道音频输出而设计。这款处理器的核心特性包括： 1. **六通道输入和输出映射**：TAS5086支持全六通道的输入和输出配置，能够灵活地处理各种音频布局和格式。 2. **音频输入/输出**：该芯片具备可选择的直流阻挡滤波器，有助于消除可能影响音频质量的直流偏置。同时，它能自动检测主时钟速率和数据流，确保音频数据的精确传输。 3. **PWM处理与采样率检测**：采用8倍过采样技术，对于44.1kHz和48kHz的采样率，实现四阶噪声整形；在88.2kHz和96kHz采样率下，实现4倍过采样；在176.4kHz和192kHz采样率下，实现2倍过采样。在32kHz和192kHz的采样率下，它甚至支持12倍过采样，以提升音质并降低噪声。 4. **兼容多种采样率**：TAS5086支持32kHz、44.1kHz、48kHz、88.2kHz、96kHz、176.4kHz和192kHz等多种常见的数字音频采样率，为不同的音频设备和标准提供了广泛的兼容性。 5. **数据格式**：该处理器可以接受16位、20位或24位输入数据，并且支持左对齐、右对齐和I2S三种数据格式，以适应各种接口需求。 6. **低失真**：TAS5086仅在单一芯片上就能实现THD（总谐波失真）小于0.06%，确保了极高的音频保真度。 7. **平坦的噪声地板**：在44.1kHz、48kHz、88.2kHz、96kHz、176.4kHz和192kHz的采样率下，其20Hz到20kHz的频段内具有平坦的噪声地板，这意味着在宽频率范围内，音频信号的纯净度得到了保证。 8. **数字去加重**：针对32kHz和48kHz的采样率，TAS5086提供了数字去加重功能，以优化这些特定采样率下的音频播放效果。 9. **六路PWM音频输出通道**：每一路输出通道都可以独立映射到任何所需的输出，增强了系统的灵活性。 10. **智能AM干扰避免**：这一特性意味着TAS5086可以自动识别并避免可能的AM广播干扰，以保持音频信号的纯净。 TI的TAS5086是一款功能强大、高度集成的数字音频处理器，适用于需要高质量多声道音频输出的应用，如家庭影院系统、专业音响设备以及高端多媒体设备等。其卓越的动态范围、低失真性能和广泛的采样率支持，使得它在音频处理领域具有显著的竞争优势。

TAS5086

www.ti.com

................................................................................................................................................... SLES131C – FEBRUARY 2005 – REVISED JUNE 2008

Table 1. TERMINAL FUNCTIONS (continued)

TERMINAL

5-V

I/O

(1)

TERMINATION

(2)

DESCRIPTION

TOLERANT

NAME NO.

Power down, active-low. PDN powers down all logic, stops all clocks, and

performs a soft stop whenever a logic low is applied. The internal

parameters are preserved through a power-down cycle, as long as RESET

PDN 10 DI 5-V Pullup

is not active. The duration for system recovery from power down is 100

ms. When released, PDN powers up all logic, starts all clocks, and

performs a soft start that returns to the previous configuration.

PLL_FLTM 5 AO PLL negative input

PLL_FLTP 6 AI PLL positive input

PWM_ 1 38 DO PWM 1 output

PWM_ 2 37 DO PWM 2 output

PWM_ 3 36 DO PWM 3 output

PWM_ 4 35 DO PWM 4 output

PWM_ 5 34 DO PWM 5 output

PWM_ 6 33 DO PWM 6 output

RESERVED 21 – RESERVED (connect to ground)

A system reset is generated by applying a logic low to this terminal.

RESET is an asynchronous control signal that restores the TAS5086 to its

default conditions, sets the VALID2 output low, and places the PWM in the

RESET 9 DI 5-V Pullup

hard-mute (M) state. Master volume is immediately set to full attenuation.

On the release of RESET, if PDN is high, the system performs a 4 – 5-ms

device initialization and sets the volume at mute.

SCL 18 DI 5-V I

C serial control clock input

Serial audio data clock (shift clock). SCLKIN is the serial audio port (SAP)

SCLK 20 DI 5-V Pulldown

input data bit clock.

SDA 17 DIO 5-V I

C serial control data interface input/output

Serial audio data 1 input is one of the serial data input ports. SDIN1

SDIN1 26 DI Pulldown

supports four discrete (stereo) data formats.

Serial audio data 2 input is one of the serial data input ports. SDIN2

SDIN2 25 DI Pulldown

supports four discrete (stereo) data formats.

Serial audio data 3 input is one of the serial data input ports. SDIN3

SDIN3 24 DI Pulldown

supports four discrete (stereo) data formats.

Serial audio data 4 input is one of the serial data input ports. SDIN4

SDIN4 23 DI Pulldown

supports four discrete (stereo) data formats.

Serial audio data 1 output is the only serial data output port. SDOUT

SDOUT 22 DI

supports I

S format only.

Soft start valid. Output indicating validity of soft-start PWM output,

VALID1 31 DO

active-high

VALID2 32 DO Output indicating validity of PWM outputs, active-high.

Voltage reference for analog supply, 1.8 V. A pinout of the internally

regulated 1.8-V power. A 0.1- µ F, low-ESR capacitor should be connected

VR_ANA 1 P

between this terminal and AVSS_PLL. This terminal must not be used to

power external devices.

Voltage reference for digital PWM core supply, 1.8 V. A pinout of the

internally regulated 1.8-V power used by digital PWM core logic. A 0.1- µ F,

VR_DIG 30 P

low-ESR

(3)

capacitor should be connected between this terminal and

DVSS_PWM. This terminal must not be used to power external devices.

Voltage reference for analog supply, 1.8 V. A pinout of the internally

regulated 1.8-V power. A 0.1- µ F, low-ESR

(3)

capacitor should be

VR_OSC 15 P

connected between this terminal and AVSS_PLL. This terminal must not

be used to power external devices.

(3) If desired, low-ESR capacitance values can be implemented by paralleling two or more ceramic capacitors of equal value. Paralleling

capacitors of equal value provides an extended high-frequency supply decoupling. This approach avoids the potential of producing

parallel resonance circuits that have been observed when paralleling capacitors of different values.

Product Folder Link(s): TAS5086

DETAILED DESCRIPTION

POWER SUPPLY

CLOCK, ERROR RATE DETECTION, AND PLL

OSCILLATOR TRIM

TAS5086

SLES131C – FEBRUARY 2005 – REVISED JUNE 2008 ...................................................................................................................................................

www.ti.com

The TAS5086 power-supply section contains regulators that provide analog and digital regulated power for

various sections of the TAS5086. The analog supply supports the analog PLL while digital supplies support the

digital PLL, the digital audio processor, the pulse width modulator, and the output control (reclocker). The

power-supply section is enabled via VREG_EN.

This module provides the timing and serial data interface for the TAS5086.

The TAS5086 is a clock slave device. It accepts MCLK, SCLK, and LRCLK.

The TAS5086 supports 64-f

MCLK for the 176.4-kHz and 192-kHz data rates.

The TAS5086 accepts a 64-f

SCLK rate for all MCLK ratios and a 48-f

SCLK rate for MCLK ratios of 192 f

and 384 f

TAS5086 checks to verify that SCLK is a specific value of 64 f

or 48 f

The TAS5086 supports a 1-f

LRCLK.

The timing relationship of these clocks to SDIN[1:4] and SDOUT is shown in subsequent sections.

The clock section uses MCLK or the internal oscillator clock (when MCLK is unstable or absent) to produce a

196-MHz PLL output.

The TAS5086 can auto-detect and set the internal clock control logic to the appropriate settings for the

frequencies of 32 kHz, normal speed (44.1 or 48 kHz), double speed (88.2 kHz or 96 kHz), and quad speed

(176.4 kHz or 192 kHz). The automatic sample rate detection can be disabled and the values set via I

The TAS5086 also supports an AM interference-avoidance mode during which the clock rate is adjusted, in

concert with the PWM sample rate converter, to produce a PWM output at 7-f

, 8-f

, or 9-f

The sample rate must be set manually during AM interference avoidance and when de-emphasis is enabled.

The TAS5086 uses an internal oscillator time base to provide reference timing information for the following

functions:

• MCLK, SCLK, and LRCLK error detection

• I

C communication when power is first applied to the device

• Automatic data-rate detection and setting (32 kHz, normal, double, and quad speed)

• Automatic MCLK rate detection and setting (64, 128, 192, 256, 384, and 512 f

)

The TAS5086 PWM processor contains an internal oscillator for PLL reference. This reduces system cost

because an external reference is not required. After each power up or reset, a oscillator trim is needed; see the

Oscillator Trim Register (0x1B) section for a detailed procedure.

Product Folder Link(s): TAS5086

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