"JEDEC标准DDR2-1066：控制时序、AC/DC特性和1066核心参数"

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DDR2-1066 JEDEC标准是一项涉及特定存储器技术的标准化规范，旨在帮助用户更好地了解和掌握DDR2控制时序、AC/DC特性和1066核心时序参数。这一标准适用于市场上所有的DDR2产品，并为制造商和消费者之间的交流和互操作性提供了一致的基础。JEDEC固态技术协会于2007年11月发布了JESD208特定DDR2-1066 SDRAM标准，该标准经过JEDEC董事会层面的准备、审查和批准，并经JEDEC法律顾问进一步审查和批准。JEDEC标准和出版物旨在通过消除制造商和购买者之间的误解，促进互换性和促进行业发展，从而为公众利益服务。该标准提供了严格的规定和技术参数，以确保DDR2-1066产品的稳定性和可靠性。通过遵循JEDEC标准，制造商和消费者可以更好地理解和满足DDR2-1066产品的技术要求，从而推动整个行业的发展。 DDR2-1066 JEDEC标准对市场上所有DDR2产品的应用具有重要意义。它不仅提供了关于DDR2控制时序和AC/DC特性的技术要求，还包括了1066核心时序参数的具体规定，为厂商和消费者提供了统一的标准，帮助他们更好地理解和满足DDR2-1066产品的技术要求。这些技术要求不仅为DDR2产品的制造提供了准确的指导，还有助于保证产品的质量和可靠性，促进了整个DDR2产品市场的有序发展。 JEDEC固态技术协会的JESD208标准在2007年11月发布，旨在为DDR2-1066 SDRAM产品的设计、生产和应用提供准确的技术规范。该标准经过严格的程序和程序，包括董事会级别的审查和批准，以及法律顾问的进一步审查和批准，确保其具有权威性和可靠性。遵循JEDEC标准，制造商和消费者可以更好地了解和掌握DDR2-1066产品的技术要求，推动DDR2产品市场的有序发展。总之，DDR2-1066 JEDEC标准是一项针对DDR2产品的权威技术规范，它对DDR2的控制时序、AC/DC特性和1066核心时序参数作出了具体的规定，有助于统一市场上所有DDR2产品的技术要求，促进整个行业的健康发展，为消费者提供更好的产品和服务。通过遵循JEDEC标准，制造商和消费者可以更好地了解和满足DDR2产品的技术要求，推动整个DDR2产品市场的发展和进步。 JEDEC标准和出版物的发布，将有助于减少技术规范方面的不确定性，促进市场交流和产品应用，从而为整个行业的发展作出积极贡献。

JEDEC Standard No. 208

Page 12

1.4 DDR2 SDRAM addressing

SSDL

Supply DLL Ground

Supply Power Supply: 1.8 V +/- 0.1 V

Supply Ground

REF

Supply Reference voltage

Table 2 — 256 Mb addressing

Configuration 64 Mb x 4 32 Mb x 8 16 Mb x 16

# of Banks 4 4 4

Bank Address BA0, BA1 BA0, BA1 BA0, BA1

Auto precharge A10/AP A10/AP A10/AP

Row Address A0 - A12 A0 - A12 A0 - A12

Column Address A0 - A9, A11 A0 - A9 A0 - A8

Page size

1 KB 1 KB 1 KB

Table 3 — 512 Mb addressing

Configuration 128 Mb x 4 64 Mb x 8 32 Mb x 16

# of Banks 4 4 4

Bank Address BA0, BA1 BA0, BA1 BA0, BA1

Auto precharge A10/AP A10/AP A10/AP

Row Address A0 - A13 A0 - A13 A0 - A12

Column Address A0 - A9, A11 A0 - A9 A0 - A9

Page size

1 KB 1 KB 2 KB

Table 4 — 1 Gb addressing

Configuration 256 Mb x 4 128 Mb x 8 64 Mb x 16

# of Banks 8 8 8

Bank Address BA0 - BA2 BA0 - BA2 BA0 - BA2

Auto precharge A10/AP A10/AP A10/AP

Row Address A0 - A13 A0 - A13 A0 - A12

Column Address A0 - A9, A11 A0 - A9 A0 - A9

Page size

1 KB 1 KB 2 KB

Table 5 — 2 Gb addressing

Configuration 512 Mb x 4 256 Mb x 8 128 Mb x 16

# of Banks 8 8 8

Bank Address BA0 - BA2 BA0 - BA2 BA0 - BA2

Auto precharge A10/AP A10/AP A10/AP

Row Address A0 - A14 A0 - A14 A0 - A13

Column Address A0 - A9, A11 A0 - A9 A0 - A9

Page size

1 KB 1 KB 2 KB

Table 1 — Ball descriptions (cont’d)

Symbol Type Function

1 Package ballout & addressing (cont’d)

1.3 Input/output functional description (cont’d)

JEDEC Standard No. 208

Page 14

2.2 Basic functionality

Read and write accesses to the DDR2 SDRAM are burst oriented; accesses start at a selected location and continue

for a burst length of four or eight in a programmed sequence. Accesses begin with the registration of an Active

command, which is then followed by a Read or Write command. The address bits registered coincident with the active

command are used to select the bank and row to be accessed (BA0-BA2 select the bank; A0-A15 select the row). The

address bits registered coincident with the Read or Write command are used to select the starting column location for

the burst access and to determine if the auto precharge command is to be issued.

Prior to normal operation, the DDR2 SDRAM must be initialized. The following sections provide detailed information

covering device initialization, register definition, command descriptions and device operation.

2.3 Power-up and initialization

DDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those

specified may result in undefined operation.

For DDR2 SDRAMs, both bits BA0 and BA1 must be decoded for Mode/Extended Mode Register Set (MRS/EMRS)

commands. Users must initialize all four Mode Registers. The registers may be initialized in any order.

2.3.1 Power-up and initialization sequence

The following sequence is required for Power-up and Initialization.

a) Either one of the following sequence is required for Power-up.

a1) While applying power, attempt to maintain CKE below 0.2 x VDDQ and ODT

at a LOW state (all other inputs

may be undefined.) The VDD voltage ramp time must be no greater than 200 ms from when VDD ramps from

300 mV to VDD min; and during the VDD voltage ramp, |VDD-VDDQ| £ 0.3 volts. Once the ramping of the

supply voltages is complete (when VDDQ crosses VDDQ min), the supply voltage specifications provided in

section 5, Table 16 Recommended DC operating conditions (SSTL_1.8), prevail.

- VDD, VDDL and VDDQ are driven from a single power converter output, AND

- VTT is limited to 0.95 V max, AND

- Vref tracks VDDQ/2, VREF must be within +/- 300 mV with respect to VDDQ/2 during supply ramp time.

- VDDQ

Š VREF must be met at all times.

a2) While applying power, attempt to maintain CKE below 0.2 x VDDQ and ODT

at a LOW state, all other inputs

may be undefined, voltage levels at I/Os and outputs must be less than VDDQ during voltage ramp time to avoid

DRAM latch-up. During the ramping of the supply voltages, VDD Š VDDL Š VDDQ must be maintained and is

applicable to both AC and DC levels until the ramping of the supply voltages is complete, which is when VDDQ

crosses VDDQ min. Once the ramping of the supply voltages is complete, the supply voltage specifications

provided in section 5, Table 16 Recommended DC operating conditions (SSTL_1.8), prevail.

- Apply VDD/VDDL before or at the same time as VDDQ.

- VDD/VDDL voltage ramp time must be no greater than 200 ms from when VDD ramps from 300 mV to VDD

min

- Apply VDDQ before or at the same time as VTT.

- The VDDQ voltage ramp time from when VDD min is achieved on VDD to when VDDQ min is achieved on

VDDQ must be no greater than 500 ms.

(Note: While VDD is ramping, current may be supplied from VDD through the DRAM to VDDQ.)

- Vref must track VDDQ/2, Vref must be within +/- 300 mv with respect to VDDQ/2 during supply ramp time.

- VDDQ Š VREF must be met at all times.

- Apply VTT.

- The VTT voltage ramp time from when VDDQ min is achieved on VDDQ to when VTT min is achieved on VTT

must be no greater than 500 ms.

b) Start clock and maintain stable condition.

c) For the minimum of 200 us after stable power (VDD, VDDL, VDDQ, VREF and VTT are between their minimum and

maximum values as stated in section 5, Table 16 Recommended DC operating conditions (SSTL_1.8)) and stable

clock (CK, CK

), then apply NOP or Deselect & take CKE HIGH.

d) Wait minimum of 400 ns then issue precharge all command. NOP or Deselect applied during 400 ns period.

e) Issue an EMRS command to EMR(2). (To issue EMRS command to EMR(2), provide LOW to BA0 and BA2, HIGH

to BA1.)

f) Issue an EMRS command to EMR(3). (To issue EMRS command to EMR(3), provide LOW to BA2, HIGH to BA0

and BA1.)

2 Functional description (cont’d)

JEDEC Standard No. 208

Page 15

g) Issue EMRS to enable DLL. (To issue DLL Enable command, provide LOW to A0, HIGH to BA0 and LOW to BA1-

BA2 and A13-A15. And A9=A8=A7=LOW must be used when issuing this command.)

h) Issue a Mode Register Set command for DLL reset.

(To issue DLL Reset command, provide HIGH to A8 and LOW to BA0-BA2, and A13-A15.)

i) Issue a precharge all command.

j) Issue 2 or more auto-refresh commands.

k) Issue a MRS command with LOW to A8 to initialize device operation. (i.e. to program operating parameters without

resetting the DLL.)

l) At least 200 clocks after step h, execute OCD Calibration (Off Chip Driver impedance adjustment).

If OCD calibration is not used, EMRS to EMR(1) to set OCD Calibration Default (A9=A8=A7=HIGH) followed by

EMRS to EMR(1) to exit OCD Calibration Mode (A9=A8=A7=LOW) must be issued with other operating parameters

of EMR(1).

m) The DDR2 SDRAM is now ready for normal operation.

*1: To guarantee ODT off, VREF must be valid and a LOW level must be applied to the ODT pin.

2.4 Programming the mode and extended mode registers

For application flexibility, burst length, burst type, CAS latency, DLL reset function, write recovery time (WR) are user

defined variables and must be programmed with a Mode Register Set (MRS) command. Additionally, DLL disable

function, driver impedance, additive CAS latency, ODT (On Die Termination), single-ended strobe, and OCD (off chip

driver impedance adjustment) are also user defined variables and must be programmed with an Extended Mode

altered by re-executing the MRS or EMRS Commands. Even if the user chooses to modify only a subset of the MR or

EMR(#) variables, all variables within the addressed register must be redefined when the MRS or EMRS commands

are issued.

MRS, EMRS and Reset DLL do not affect array contents, which means re-initialization including those can be

executed at any time after power-up without affecting array contents.

2.4.1 DDR2 SDRAM mode register (MR)

The mode register stores the data for controlling the various operating modes of DDR2 SDRAM. It controls CAS

latency, burst length, burst sequence, test mode, DLL reset, WR and various vendor specific options to make DDR2

SDRAM useful for various applications. The default value of the mode register is not defined, therefore the mode

on CS

, RAS, CAS, WE, BA0 and BA1, while controlling the state of address pins A0 - A15. The DDR2 SDRAM should

be in all bank precharge state with CKE already HIGH prior to writing into the mode register. The mode register set

command cycle time (tMRD) is required to complete the write operation to the mode register. The mode register

contents can be changed using the same command and clock cycle requirements during normal operation as long as

all banks are in the precharge state. The mode register is divided into various fields depending on functionality. Burst

length is defined by A0 - A2 with options of 4 and 8 bit burst lengths. The burst length decodes are compatible with

DDR SDRAM. Burst address sequence type is defined by A3, CAS

latency is defined by A4 - A6. The DDR2 does not

support half clock latency mode. A7 is used for test mode. A8 is used for DLL reset. A7 must be set to LOW for normal

MRS operation. Write recovery time WR is defined by A9 - A11. Refer to the table for specific codes.

/CK

Command

MR RE

MR EM

DLL

OCD

CAL.

400

tRF

tOI

min 200

tCL

tCH

tIS

Figure 13 — Initialization sequence after power-up

2.3 Power-up and initialization (cont’d)

2.3.1 Power-up and initialization sequence (cont’d)

JEDEC Standard No. 208

Page 16

2.4.2 DDR2 SDRAM extended mode registers (EMR(#))

2.4.2.1 EMR(1)

The extended mode register(1) stores the data for enabling or disabling the DLL, output driver strength, additive latency, ODT, DQS

disable, OCD program, RDQS enable. The default value of the extended mode register(1) is not defined, therefore the extended

mode register(1) must be programmed during initialization for proper operation. The extended mode register(1) is written by asserting

LOW on CS

, RAS, CAS, WE, HIGH on BA0 and LOW on BA1, while controlling the states of address pins A0 - A15. The DDR2

SDRAM should be in all bank precharge with CKE already HIGH prior to writing into the extended mode register(1). The mode

register set command cycle time (tMRD) must be satisfied to complete the write operation to the extended mode register(1).

Extended mode register(1) contents can be changed using the same command and clock cycle requirements during normal

operation as long as all banks are in the precharge state. A0 is used for DLL enable or disable. A1 is used for enabling a reduced

strength output driver. A3 - A5 determines the additive latency, A7 - A9 are used for OCD control, A10 is used for DQS

disable and

A11 is used for RDQS enable. A2 and A6 are used for ODT setting.

2.4.2.2 DLL enable/disable

The DLL must be enabled for normal operation. DLL enable is required during power-up and initialization, and upon returning to

normal operation after having the DLL disabled. The DLL is automatically disabled when entering self refresh operation and is

automatically re-enabled upon exit of self refresh operation. Any time the DLL is enabled (and subsequently reset), 200 clock cycles

must occur before a Read command can be issued to allow time for the internal clock to be synchronized with the external clock.

Failing to wait for synchronization to occur may result in a violation of the tAC or tDQSCK parameters.

2.4.2.3 EMR(1) programming

Figure 15 shows the EMR(1) programming.

Address Field

A7 mode

0Normal

1Test

A3 Burst Type

0 Sequential

1 Interleave

A8 DLL Reset

0No

1Yes

Mode Register

TM CAS

Latency BTDLL

Write recovery for autoprecharge

A11 A10 A9 WR(cycles)

0 0 0 Reserved

001 2

010 3

011 4

100 5

101 6

110 7

111 8

~ A

Burst Length

A2 A1 A0 BL

0104

0118

BA1 BA0

MRS mode

00 MR

01 EMR(1)

10 EMR(2)

11 EMR(3)

A12

Active power down

exit time

0 Fast exit (use t

XARD)

1 Slow exit (use t

XARDS)

A6 A5 A4 CAS Latency

0 0 0 Reserved

0 0 1 Reserved

0 1 0 2(Optional)

0 1 1 3(Optional)

100 4

101 5

110 6

111 7

Figure 14 — DDR2 SDRAM mode register set (MRS)

NOTE 1 BA2 and A13-A15 are reserved for future use and must be set to 0 when programming the MR.

NOTE 2 For DDR2-1066, WR min is determined by tCK(avg) max and WR max is determined by tCK(avg) min. WR

in clock cycles is calculated by dividing tWR (in ns) by tCK (in ns) and rounding up to the next integer. WR[cycles] =

RU{ tWR[ns] / tCK(avg)[ns] }, where RU stands for round up. The mode register must be programmed to this value.

This is also used with tRP to determine tDAL.

2.4.2 DDR2 SDRAM extended mode registers (EMR(#)) (cont’d)

2.4.2.1 EMR(1) (cont’d)

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