Winbond W25X系列串口Flash内存详细规格与功能介绍

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本文档详细介绍了Winbond W25X系列的1M、2M、4M和8M位串口闪存存储器。W25X系列的特点在于它们具有4KB的扇区大小和双输出SPI接口，这使得它们在小型尺寸和高效数据传输方面具有优势。该系列包括了不同的封装类型，如SOIC150-mil、SOIC208-mil、PDIP300-mil以及WSON6x5-mm，满足不同应用场合的需求。文档首先概述了内存的通用描述和特性，包括其高速度和可靠性。接着，详细解释了各引脚配置，如ChipSelect（/CS）、Serial Data Output (DO)、WriteProtect（/WP）、HOLD（/HOLD）、Serial Clock (CLK) 和 Serial Data Input/Output (DIO)，这些都是SPI通信的关键信号线。SPI操作被分成几个部分来讲解，包括SPI模式、双输出SPI模式以及Hold功能的使用，这有助于用户理解和配置存储器。 Write Protection功能是文档的核心部分，它包括WriteProtect Features，如如何启用和禁用写保护，以及Block Protect Bits（BP2, BP1, BP0）和Top/Bottom Block Protect（TB）的设置，以确保数据的安全性。此外，还提到了控制和状态寄存器，这些寄存器对操作者来说非常重要，因为它们用于监控设备状态（如BUSY标志），控制写入操作（WriteEnableLatch, WEL），以及管理存储器保护（Status Register Protect, SRP）。文档还提供了Block Diagram，展示了存储器内部结构和组件间的连接，这对于硬件设计者理解硬件工作原理很有帮助。整体而言，这份资料是关于如何设计和使用W25X系列串口闪存的重要参考资料，无论是进行嵌入式系统开发，还是进行存储设备的维护或升级，都是不可或缺的工具。

W25X10, W25X20, W25X40, W25X80

Publication Release Date: June 21, 2007

- 9 - Revision L

9. FUNCTIONAL DESCRIPTION

9.1 SPI OPERATIONS

9.1.1 SPI Modes

The W25X10/20/40/80 is accessed through an SPI compatible bus consisting of four signals: Serial

Clock (CLK), Chip Select (/CS), Serial Data Input/Output (DIO) and Serial Data Output (DO). Both SPI

bus operation Modes 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and

Mode 3 concerns the normal state of the CLK signal when the SPI bus master is in standby and data

is not being transferred to the Serial Flash. For Mode 0 the CLK signal is normally low. For Mode 3 the

CLK signal is normally high. In either case data input on the DIO pin is sampled on the rising edge of

the CLK. Data on the DO and DIO pins are clocked out on the falling edge of CLK.

9.1.2 Dual Output SPI

The W25X10/20/40/80 supports Dual output operation when using the “Fast Read with Dual Output”

(3B hex) instruction. This feature allows data to be transferred from the Serial Flash memory at twice

the rate possible with the standard SPI. This instruction is ideal for quickly downloading code from

Flash to RAM upon power-up (code-shadowing) or for applications that cache code-segments to RAM

for execution. The Dual output feature simply allows the SPI input pin to also serve as an output

during this instruction. All other operations use the standard SPI interface with single output signal.

9.1.3 Hold Function

The /HOLD signal allows the W25X10/20/40/80 operation to be paused while it is actively selected

(when /CS is low). The /HOLD function may be useful in cases where the SPI data and clock signals

are shared with other devices. For example, consider if the page buffer was only partially written when

a priority interrupt requires use of the SPI bus. In this case the /HOLD function can save the state of

the instruction and the data in the buffer so programming can resume where it left off once the bus is

available again.

To initiate a /HOLD condition, the device must be selected with /CS low. A /HOLD condition will

activate on the falling edge of the /HOLD signal if the CLK signal is already low. If the CLK is not

already low the /HOLD condition will activate after the next falling edge of CLK. The /HOLD condition

will terminate on the rising edge of the /HOLD signal if the CLK signal is already low. If the CLK is not

already low the /HOLD condition will terminate after the next falling edge of CLK.

During a /HOLD condition, the Serial Data Output (DO) is high impedance, and Serial Data

Input/Output (DIO) and Serial Clock (CLK) are ignored. The Chip Select (/CS) signal should be kept

active (low) for the full duration of the /HOLD operation to avoid resetting the internal logic state of the

device.

W25X10, W25X20, W25X40, W25X80

- 10 -

9.2 WRITE PROTECTION

Applications that use non-volatile memory must take into consideration the possibility of noise and

other adverse system conditions that may compromise data integrity. To address this concern the

W25X10/20/40/80 provides several means to protect data from inadvertent writes.

9.2.1 Write Protect Features

• Device resets when VCC is below threshold.

• Time delay write disable after Power-up.

• Write enable/disable instructions.

• Automatic write disable after program and erase.

• Software write protection using Status Register.

• Hardware write protection using Status Register and /WP pin.

• Write Protection using Power-down instruction.

Upon power-up or at power-down the W25X10/20/40/80 will maintain a reset condition while VCC is

below the threshold value of V

WI, (See Power-up Timing and Voltage Levels and Figure 20). While

reset, all operations are disabled and no instructions are recognized. During power-up and after the

VCC voltage exceeds V

WI, all program and erase related instructions are further disabled for a time

delay of t

PUW. This includes the Write Enable, Page Program, Sector Erase, Block Erase, Chip Erase

and the Write Status Register instructions. Note that the chip select pin (/CS) must track the VCC

supply level at power-up until the VCC-min level and t

VSL time delay is reached. If needed a pull-up

resister on /CS can be used to accomplish this.

After power-up the device is automatically placed in a write-disabled state with the Status Register

Write Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Page

Program, Sector Erase, Chip Erase or Write Status Register instruction will be accepted. After

completing a program, erase or write instruction the Write Enable Latch (WEL) is automatically

cleared to a write-disabled state of 0.

Software controlled write protection is facilitated using the Write Status Register instruction and setting

the Status Register Protect (SRP) and Block Protect (TB, BP2, BP1, and BP0) bits. These Status

with the Write Protect (/WP) pin, changes to the Status Register can be enabled or disabled under

hardware control. See Status Register for further information.

Additionally, the Power-down instruction offers an extra level of write protection as all instructions are

ignored except for the Release Power-down instruction.

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