CycloneIV收发器架构详解：官方最新资料

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本文档主要介绍了Cyclone IV Transceivers架构，这是Altera公司的一款FPGA（Field-Programmable Gate Array）系列——CYCLONE IV的一部分。CYCLONE IV是 Altera针对高性能和低功耗应用设计的第四代FPGA产品线，它融合了先进的逻辑处理能力和高效的数据传输能力。 Cyclone IV Transceivers架构的关键特点包括： 1. **高性能接口支持**：CYIV-52001-3.7型号可能指的是特定的器件，它提供了一系列高速串行和并行接口，如LVDS、SSTL等，用于实现高速数据传输，满足现代通信系统的需求。 2. **集成度与灵活性**：Cyclone IV的设计集成了收发器模块，使得信号处理和数据转换可以在同一片FPGA上完成，减少了外部接口组件的需求，提高了系统整体的集成度和灵活性。 3. **低功耗设计**：为了适应能源效率日益增长的需求，Cyclone IV Transceivers采用了节能技术，例如在不活动时自动进入休眠模式，以减少功率消耗。 4. **标准符合性**：文档提及了ISO 9001:2008质量管理体系注册，表明Altera对其产品的制造过程有严格的管理和控制，确保产品质量和一致性。 5. **保修政策**：Altera为消费者提供了标准保修服务，但同时也指出可能会根据需要对产品和服务进行更新，提醒用户在使用前应获取最新的设备规格。 6. **技术支持与反馈**：文档鼓励用户提供反馈，并承诺在February 2015版的《Cyclone IV设备手册》中提供了详细的资料，这表明Altera重视与客户的互动，不断优化产品性能。 7. **知识产权保护**：文中提到的商标和专利信息强调了Altera对知识产权的尊重，以及其在法律保护下的权利。阅读这份文档有助于理解Cyclone IV Transceivers的内部结构、功能特性和使用注意事项，对于那些从事FPGA设计或需要利用该架构进行高速数据传输的工程师来说，是极其重要的参考资料。

1–16 Chapter 1: Cyclone IV Transceivers Architecture

Receiver Channel Datapath

Cyclone IV Device Handbook, February 2015 Altera Corporation

Volume 2

Actual lock time depends on the transition density of the incoming data and the ppm

difference between the receiver input reference clock and the upstream transmitter

reference clock.

Transition from the LTD state to the LTR state occurs when either of the following

conditions is met:

■ Signal detection circuitry indicates the absence of valid signal levels at the receiver

input buffer. This condition is valid for PCI Express (PIPE) mode only. CDR

transitions are not dependent on signal detection circuitry in other modes.

■ The recovered clock is not within the configured ppm frequency threshold setting

with respect to CDR clocks from multipurpose PLLs.

In automatic lock mode, the switch from LTR to LTD states is indicated by the

assertion of the

rx_freqlocked

signal and the switch from LTD to LTR states indicated

by the de-assertion of the

rx_freqlocked

signal.

Manual Lock Mode

State transitions are controlled manually by using

rx_locktorefclk

and

rx_locktodata

ports. The LTR/LTD controller sets the CDR state depending on the

logic level on the

rx_locktorefclk

and

rx_locktodata

ports. This mode provides the

flexibility to control the CDR for a reduced lock time compared to the automatic lock

mode. In automatic lock mode, the LTR/LTD controller relies on the ppm detector

and the phase relationship detector to set the CDR in LTR or LTD mode. The ppm

detector and phase relationship detector reaction times can be too long for some

applications that require faster CDR lock time.

In manual lock mode, the

rx_freqlocked

signal is asserted when the CDR is in LTD

state and de-asserted when CDR is in LTR state. For descriptions of

rx_locktorefclk

and

rx_locktodata

port controls, refer to Table 1–27 on page 1–87.

1 If you do not enable the optional

rx_locktorefclk

and

rx_locktodata

ports, the

Quartus II software automatically configures the LTR/LTD controller in automatic

lock mode.

f The recommended transceiver reset sequence varies depending on the CDR lock

mode. For more information about the reset sequence recommendations, refer to the

Reset Control and Power Down for Cyclone IV GX Devices chapter.

Deserializer

The deserializer converts received serial data from the receiver input buffer to parallel

8- or 10-bit data. Serial data is assumed to be received from the LSB to the MSB. The

deserializer operates with the high-speed recovered clock from the CDR with the

frequency at half of the serial data rate.

Chapter 1: Cyclone IV Transceivers Architecture 1–17

Receiver Channel Datapath

February 2015 Altera Corporation Cyclone IV Device Handbook,

Volume 2

Word Aligner

Figure 1–16 shows the word aligner block diagram. The word aligner receives parallel

data from the deserializer and restores the word boundary based on a pre-defined

alignment pattern that must be received during link synchronization. The word

aligner supports three operational modes as listed in Table 1–3.

Manual Alignment Mode

In manual alignment mode, the

rx_enapatternalign

port controls the word aligner

with either an 8- or 10-bit data width setting.

The 8-bit word aligner is edge-sensitive to the

rx_enapatternalign

signal. A rising

edge on

rx_enapatternalign

signal after deassertion of the

rx_digitalreset

signal

triggers the word aligner to look for the word alignment pattern in the received data

stream. It updates the word boundary if it finds the word alignment pattern in a new

word boundary. Any word alignment pattern received thereafter in a different word

boundary causes the word aligner to re-align to the new word boundary only if there

is a rising edge in the

rx_enapatternalign

signal.

The 10-bit word aligner is level-sensitive to the

rx_enapatternalign

signal. The word

aligner looks for the programmed 7-bit or 10-bit word alignment pattern or its

complement in the received data stream, if the

rx_enapatternalign

signal is held

high. It updates the word boundary if it finds the word alignment pattern in a new

word boundary. If the

rx_enapatternalign

signal is deasserted, the word aligner

maintains the current word boundary even when it receives the word alignment

pattern in a new word boundary.

Figure 1–16. Word Aligner Block Diagram

Word Aligner

Bit-Slip

Circuitry

Synchronization

State Machine

Manual

Alignment

rx_bitslipboundaryselectout

Run Length

Violation

rx_rlv

parallel data to

next PCS block

rx_syncstatus

rx_patterndetect

Receiver

Polarity

Inversion

rx_enapatternalign

data from

deserializer

rx_bitslip

rx_invpolarity

rx_revbitorderwa

Receiver

Bit

Reversal

Table 1–3. Word Aligner Modes

Modes PMA-PCS Interface Widths

Allowed Word Alignment

Pattern Lengths

Manual Alignment

8-bit 16 bits

10-bit 7 or 10 bits

Bit-Slip

8-bit 16 bits

10-bit 7 or 10 bits

Automatic Synchronization State

Machine

10-bit 7 or 10 bits

1–18 Chapter 1: Cyclone IV Transceivers Architecture

Receiver Channel Datapath

Cyclone IV Device Handbook, February 2015 Altera Corporation

Volume 2

After updating the word boundary, word aligner status signals (

rx_syncstatus

and

rx_patterndetect

) are driven high for one parallel clock cycle synchronous to the

most significant byte of the word alignment pattern. The

rx_syncstatus

and

rx_patterndetect

signals have the same latency as the datapath and are forwarded to

the FPGA fabric to indicate the word aligner status. Any word alignment pattern

received thereafter in the same word boundary causes only the

rx_patterndetect

signal to go high for one clock cycle.

Figure 1–17 shows the manual alignment mode word aligner operation in 10-bit data

width mode. In this example, a /K28.5/ (10'b0101111100) is specified as the word

alignment pattern.

The word aligner aligns to the /K28.5/ alignment pattern (red) in cycle n because the

rx_enapatternalign

signal is asserted high. The

rx_syncstatus

signal goes high for

one clock cycle indicating alignment to a new word boundary. The

rx_patterndetect

signal also goes high for one clock cycle to indicate initial word alignment.

At time n + 1, the

rx_enapatternalign

signal is deasserted to instruct the word

aligner to lock the current word boundary.

The alignment pattern is detected again (green) in a new word boundary across cycles

n + 2 and n + 3. The word aligner does not align to this new word boundary because

the

rx_enapatternalign

signal is held low.

The /K28.5/ word alignment pattern is detected again (blue) in the current word

boundary during cycle n + 5 causing the

rx_patterndetect

signal to go high for one

parallel clock cycle.

1 If the word alignment pattern is known to be unique and does not appear between

word boundaries, you can hold the

rx_enapatternalign

signal constantly high

because there is no possibility of false word alignment. If there is a possibility of the

word alignment pattern occurring across word boundaries, you must control the

rx_enapatternalign

signal to lock the word boundary after the desired word

alignment is achieved to avoid re-alignment to an incorrect word boundary.

Figure 1–17. Word Aligner in 10-bit Manual Alignment Mode

rx_enapatternalign

rx_clock

n n + 1 n + 2 n + 3 n + 4

rx_patterndetect

rx_syncstatus

rx_dataout[9..0]

111110000

MSB LSB MSB LSB

0101111100 111110000 1111001010 1000000101 111110000 0101111100

n + 5

Chapter 1: Cyclone IV Transceivers Architecture 1–19

Receiver Channel Datapath

February 2015 Altera Corporation Cyclone IV Device Handbook,

Volume 2

Bit-Slip Mode

In bit-slip mode, the

rx_bitslip

port controls the word aligner operation. At every

rising edge of the

rx_bitslip

signal, the bit-slip circuitry slips one bit into the

received data stream, effectively shifting the word boundary by one bit. When the

received data after bit-slipping matches the programmed word alignment pattern, the

rx_patterndetect

signal is driven high for one parallel clock cycle.

1 You can implement a bit-slip controller in the user logic that monitors either the

rx_patterndetect

signal or the receiver data output (

rx_dataout

), and controls the

rx_bitslip

port to achieve word alignment.

Figure 1–18 shows an example of the word aligner configured in bit-slip mode. For

this example, consider that 8'b11110000 is received back-to-back and

16'b0000111100011110 is specified as the word alignment pattern. A rising edge on the

rx_bitslip

signal at time n + 1 slips a single bit 0 at the MSB position, forcing the

rx_dataout

to 8'b01111000. Another rising edge on the

rx_bitslip

signal at time n + 5

forces rx_dataout to 8'b00111100. Another rising edge on the

rx_bitslip

signal at time

n + 9 forces

rx_dataout

to 8'b00011110. Another rising edge on the

rx_bitslip

signal

at time n + 13 forces the

rx_dataout

to 8'b00001111. At this instance,

rx_dataout

cycles n + 12 and n + 13 is 8'b00011110 and 8'b00001111, respectively, which matches

the specified 16-bit alignment pattern 16'b0000111100011110. This results in the

assertion of the

rx_patterndetect

signal.

Automatic Synchronization State Machine Mode

In automatic synchronization state machine mode, the word aligner achieves

synchronization after receiving a specific number of synchronization code groups,

and falls out of synchronization after receiving a specific number of erroneous code

groups. This mode provides hysteresis during link synchronization, which is required

by protocols such as PCIe, GbE, XAUI, and Serial RapidIO.

1 This mode is only supported using the 8B/10B encoded data with 10-bit input to the

word aligner.

Figure 1–18. Word Aligner Configured in Bit-Slip Mode

01111000

11110000

00111100 00011110 00001111

rx_clkout

rx_datain7..0]

rx_dataout[7..0]

rx_bitslip

rx_patterndetect

11110000

n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 n + 8 n + 9 n + 10 n + 11 n + 12 n + 13 n + 14

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