ARM架构详览：程序员与底层开发者的权威指南

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"ARM体系结构英文手册（ARM Architecuture Reference Manual）是针对程序员和底层开发人员设计的一套详尽的技术指南。这份文档由ARM Limited自1996年至2005年发布，版权受到严格保护。手册包含了ARM架构的深入介绍，详细解释了ARM处理器的设计原则、指令集、寄存器组以及其在嵌入式和移动计算领域的应用。该文档的核心内容涵盖了ARM架构的各个方面，包括但不限于处理器内核特性、数据类型、寻址方式、流水线设计、异常处理、内存管理等。此外，手册还提供了ARM指令集的详细介绍，这对于理解程序如何在ARM平台上执行至关重要。它强调了ARM技术的持续发展和改进，表明用户所使用的ARM产品可能包含最新的优化和增强功能。值得注意的是，手册中的某些部分具有专属性，提到了ARM品牌的多个商标，如ARM、Thumb、StrongARM、ARM7TDMI等，这些都是ARM Limited的注册商标。同时，手册中提到的其他产品或服务可能是各自所有者拥有的商标。对于用户来说，这本手册不仅是一份技术文档，也揭示了与ARM生态系统中不同组件的交互方式。许可证方面，ARM向读者授予了一项永久、非独家、不可转让的全球免费许可，允许用户根据手册中的描述使用ARM架构，但需遵守文档中列出的特定条款和条件。这意味着用户可以在不支付额外费用的情况下，合法地在他们的项目中采用ARM技术。 ARM Architecuture Reference Manual是开发人员不可或缺的参考资料，它为理解和利用ARM架构提供了全面而深入的知识，帮助他们在实际开发中实现高效和兼容的代码编写。"

Preface

• The restriction that multiplication destination registers should be different from their source registers

is removed in ARMv6.

• In ARMv5, the

LDM

(2) and

STM

(2) ARM instructions have restrictions on the use of banked registers

by the immediately following instruction. These restrictions are removed from ARMv6.

• The rules determining which PSR bits are updated by an

MSR

instruction are clarified and extended to

cover the new PSR bits defined in ARMv6.

• In ARMv5, the Thumb

MOV

instruction behavior varies according to the registers used (see note). Two

changes are made in ARMv6.

— The restriction about the use of low register numbers in the

MOV

(3) instruction encoding is

removed.

— In order to make the new side-effect-free

MOV

instructions available to the assembler language

programmer without changing the meaning of existing assembler sources, a new assembler

syntax

CPY Rd,Rn

is introduced. This always assembles to the

MOV

(3) instruction regardless of

whether Rd and Rn are high or low registers.

Note

In ARMv5, the Thumb

MOV Rd,Rn

instructions have the following properties:

• If both Rd and Rn are low registers, the instruction is the

MOV

(2) instruction. This instruction sets the

N and Z flags according to the value transferred, and sets the C and V flags to 0.

• If either Rd or Rn is a high register, the instruction is the

MOV

(3) instruction. This instruction leaves

the condition flags unchanged.

This situation results in behavior that varies according to the registers used. The

MOV

(2) side-effects also limit

compiler flexibility on use of pseudo-registers in a global register allocator.

Naming of ARM/Thumb architecture versions

To name a precise version and variant of the ARM/Thumb architecture, the following strings are

concatenated:

1. The string

ARMv

2. The version number of the ARM instruction set.

3. Variant letters of the included variants.

4. In addition, the letter P is used after x to denote the exclusion of several instructions in the

ARMv5TExP variant.

The table Architecture versions on page xvii lists the standard names of the current (not obsolete)

ARM/Thumb architecture versions described in this manual. These names provide a shorthand way of

describing the precise instruction set implemented by an ARM processor. However, this manual normally

uses descriptive phrases such as T variants of architecture version 4 and above to avoid the use of lists of

architecture names.

Preface

Part B - Memory and System Architectures

Part B describes standard memory system features that are normally implemented by the System Control

coprocessor (coprocessor 15) in an ARM-based system. It contains the following chapters:

Chapter B1 Gives a brief overview of this part of the manual.

Chapter B2 The memory order model.

Chapter B3 Gives a general description of the System Control coprocessor and its use.

Chapter B4 Describes the standard ARM memory and system architecture based on the use of a Virtual

Memory System Architecture (VMSA) based on a Memory Management Unit (MMU).

Chapter B5 Gives a description of the simpler Protected Memory System Architecture (PMSA) based on

a Memory Protection Unit (MPU).

Chapter B6 Gives a description of the standard ways to control caches and write buffers in ARM

memory systems. This chapter is relevant both to systems based on an MMU and to systems

based on an MPU.

Chapter B7 Describes the Tightly Coupled Memory (TCM) architecture option for level 1 memory.

Chapter B8 Describes the Fast Context Switch Extension and Context ID support (ARMv6 only).

Part C - Vector Floating-point Architecture

Part C describes the Vector Floating-point (VFP) architecture. This is a coprocessor extension to the ARM

architecture designed for high floating-point performance on typical graphics and DSP algorithms.

Chapter C1 Gives a brief overview of the VFP architecture and information about its compliance with

the IEEE 754-1985 floating-point arithmetic standard.

Chapter C2 Describes the floating-point formats supported by the VFP instruction set, the floating-point

general-purpose registers that hold those values, and the VFP system registers.

Chapter C3 Describes the VFP coprocessor instruction set, organized by type of instruction.

Chapter C4 Contains detailed reference material on the VFP coprocessor instruction set, organized

alphabetically by instruction mnemonic.

Chapter C5 Contains detailed reference material on the addressing modes used by VFP instructions.

One of these is a traditional addressing mode, generating addresses for load/store

instructions. The remainder specify how the floating-point general-purpose registers and

instructions can be used to hold and perform calculations on vectors of floating-point values.

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ARM架构详览：程序员与底层开发者的权威指南

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