内存屏障：硬件视角下的软件优化解析

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"内存屏障是计算机硬件和软件交互的关键机制，用于确保在多处理器系统（SMP）中的同步原语正确执行。它们的存在是由于CPU为了优化性能而进行的内存引用重排序，但这种重排序可能导致内存访问顺序的不确定性，从而影响同步操作的正确性。本文将深入探讨内存屏障的原理，以及它们与CPU缓存、一致性协议的关系。 1. CPU缓存结构： CPU缓存是位于CPU与主内存之间的小型高速存储器，旨在减少CPU访问主内存的延迟。缓存通常分为多个层次（如L1、L2、L3），每个层次具有不同的大小和速度。缓存的工作基于局部性原理，即程序倾向于在短时间内访问同一块内存区域。缓存通过缓存行（Cache Line）来存储和管理数据，当CPU需要读取或写入数据时，会首先查找缓存，如果数据在缓存中，称为缓存命中；否则，称为缓存未命中，需要从主内存中加载。 2. 缓存一致性协议：在多处理器系统中，每个CPU都有自己的缓存，当多个CPU同时修改共享内存时，必须保证所有CPU对内存状态有一致的视图。为此，引入了缓存一致性协议，如MESI（Modified, Exclusive, Shared, Invalidated）或MOESI（Modified, Owned, Exclusive, Shared, Invalidated）。这些协议规定了如何处理缓存行的状态变化和在CPU间传播这些变化，以保持数据的一致性。 3. 存储缓冲区与无效队列：现代CPU在写操作时可能不会立即更新主内存，而是将数据暂存到存储缓冲区中，等到合适时机再批量写入。同时，当一个CPU修改了缓存中的数据，需要通知其他CPU其缓存中对应数据已失效，这涉及到无效队列的管理。这些机制虽然提高了性能，但也可能导致数据的可见性问题。 4. 内存屏障的作用：内存屏障是一种指令，用于阻止特定内存操作的重排序。它确保在屏障前的操作完成并使其他处理器看到这些操作后，才执行屏障后的操作。对于Java程序员来说，内存屏障体现在 volatile 关键字的使用上，它可以强制内存操作的顺序，保证多线程环境中的可见性和有序性。总结来说，内存屏障是应对CPU缓存优化和数据一致性挑战的必要工具。它们虽然带来了复杂性，但确保了在高性能和可扩展性的系统中，软件能够正确地执行同步操作，维持数据的一致性和正确性。"

address 0, it enters the “shared” state in CPU 0’s

cache, and is still valid in memory. CPU 3 also loads

the data at address 0, so that it is in the “shared”

state in both CPUs’ caches, and is still valid in mem-

ory. Next CPU 0 loads some other cache line (at ad-

dress 8), which forces the data at address 0 out of its

cache via an invalidation, replacing it with the data

at address 8. CPU 2 now does a load from address 0,

but this CPU realizes that it will soon need to store

to it, and so it uses a “read invalidate” message in

order to gain an exclusive copy, invalidating it from

CPU 3’s cache (though the copy in memory remains

up to date). Next CPU 2 does its anticipated store,

changing the state to “modiﬁed”. The copy of the

data in memory is now out of date. CPU 1 does an

atomic increment, using a “read invalidate” to snoop

the data from CPU 2’s cache and invalidate it, so that

the copy in CPU 1’s cache is in the “modiﬁed” state

(and the copy in memory remains out of date). Fi-

nally, CPU 1 reads the cache line at address 8, which

uses a “writeback” message to push address 0’s data

back out to memory.

Note that we end with data in some of the CPU’s

caches.

Quick Quiz 5: What sequence of operations

would put the CPUs’ caches all back into the “in-

valid” state?

3 Stores Result in Unnecessary

Stalls

Although the cache structure shown in Figure 1 pro-

vides good performance for repeated reads and writes

from a given CPU to a given item of data, its perfor-

mance for the ﬁrst write to a given cache line is quite

poor. To see this, consider Figure 4, which shows a

timeline of a write by CPU 0 to a cacheline held in

CPU 1’s cache. Since CPU 0 must wait for the cache

line to arrive before it can write to it, CPU 0 must

stall for an extended period of time.

The time required to transfer a cache line from one CPU’s

cache to another’s is typically a few orders of magnitude more

than that required to execute a simple register-to-register in-

struction.

CPU 0 CPU 1

Write

Acknowledgement

Invalidate

Stall

Figure 4: Writes See Unnecessary Stalls

But there is no real reason to force CPU 0 to stall

for so long — after all, regardless of what data hap-

pens to be in the cache line that CPU 1 sends it, CPU

0 is going to unconditionally overwrite it.

3.1 Store Buﬀers

One way to prevent this unnecessary stalling of writes

is to add “store buﬀers” between each CPU and its

cache, as shown in Figure 5. With the addition of

these store buﬀers, CPU 0 can simply record its write

in its store buﬀer and continue executing. When the

cache line does ﬁnally make its way from CPU 1 to

CPU 0, the data will be moved from the store buﬀer

to the cache line.

However, there are complications that must be ad-

dressed, which are covered in the next two sections.

3.2 Store Forwarding

To see the ﬁrst complication, a violation of self-

consistency, consider the following code with vari-

ables “a” and “b” both initially zero, and with the

cache line containing variable “a” initially owned by

CPU 1 and that containing “b” initially owned by

CPU 0:

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