NUC1xx系列技术手册：2010年V1.03版，Cortex-M0微控制器详解

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本资源是关于NUC1XX系列的技术参考手册，发布日期为2010年6月7日，版本为V1.03，由Nuvoton Technology Corporation提供。这是一份详尽的文档，专为基于NuMicro Cortex-M0微控制器的系统设计提供参考。手册强调，所有信息和规格可能未经通知即会变更，因此在设计和应用时需保持更新。该手册分为几个主要部分： 1. **概述** (General Description): 这部分介绍了NUC1XX系列的核心特性，可能涵盖了处理器架构、功耗特性和主要应用场景。它旨在帮助用户理解和选择合适的Nuvoton微控制器型号，如NUC101、NUC100、NUC120、NUC130和NUC140。 2. **功能特性** (Features): - **NUC101**: 特点可能包括低功耗、高性能、特定的I/O引脚配置和集成的外设，如ADC、DAC或USB接口。 - **NUC100**: 可能强调了基本特性，但相比NUC101可能会有稍低的性能或功耗优化。 - **NUC120**: 可能提供更高级的功能，如更高的处理速度、更大的存储容量或额外的安全特性。 - **NUC130** 和 **NUC140**: 进一步增强的性能，可能包括更先进的处理器核心、扩展的外设支持或更高级别的通信能力。 3. **部件信息列表与引脚配置** (Parts Information List and Pin Configuration): 这部分详细列出了每款产品的具体规格，如封装类型、引脚定义、电源需求以及与其他组件的连接方式。这对于硬件设计工程师来说至关重要，他们需要准确地理解如何将这些微控制器集成到电路板上。这份技术参考手册是开发人员和设计者在设计基于NUC1XX系列微控制器系统时不可或缺的参考资料，提供了产品特性、选型指导和电气连接信息，确保用户能够充分利用这些设备的优势，并了解可能的限制和更新。在实际应用中，务必确保查阅最新的版本以获取最准确的信息。

NUC1XX Series Technical Reference Manual

Publication Release Date: June 7, 2010

- 16 - Revision V1.03

• I

– Two sets of I

C device.

– Master/Slave up to 1Mbit/s

– Bidirectional data transfer between masters and slaves

– Multi-master bus (no central master).

– Arbitration between simultaneously transmitting masters without corruption of serial data on

the bus

– Serial clock synchronization allows devices with different bit rates to communicate vian one

serial bus.

– Serial clock synchronization can be used as a handshake mechanism to suspend and resume

serial transfer.

– Programmable clocks allow versatile rate control.

– I2C-bus controllers support multiple address recognition ( two slave address with mask option)

• I

– Interface with external audio CODEC

– Operate as either master or slave mode

– Capable of handling 8, 16, 24 and 32 bit word sizes

– Mono and stereo audio data supported

– I

S and MSB justified data format supported

– Two 8 word FIFO data buffers are provided, one for transmit and one for receive

– Generates interrupt requests when buffer levels cross a programmable boundary

– Support two DMA requests, one for transmit and one for receive

• USB 2.0 Full-Speed Device

– One set of USB 2.0 FS Device 12Mbps

– On-chip USB Transceiver.

– Provide 1 interrupt source with 4 interrupt events.

– Support Control, Bulk In/Out, Interrupt and Isochronous transfers.

– Auto suspend function when no bus signaling for 3 ms.

– Provide 6 programmable endpoints.

– Include 512 Bytes internal SRAM as USB buffer.

– Provide remote wakeup capability.

– Support PDMA mode

• ADC

– 12-bit SAR ADC with 800ksps

– Up to 8-ch single-end mode or 4-ch differential mode

– Single scan/single cycle scan/continuous scan

– Each channel with individual result register

– Scan on enabled channels

– Threshold voltage detection

– Conversion start by S/W, external pins

– Support PDMA Mode

• Analog Comparator

– Two analog comparator modules

– External input or internal bandgap voltage selectable at negative node

– Interrupt when compare result change

– Power down wake up

NUC1XX Series DATA SHEET

Publication Release Date: June 7, 2010

- 19 - Revision V1.03

• Timers

– 4 sets of 24-bit timer with 8-bit prescaler.

– Counter auto reload.

• Watch Dog Timer

– Default ON/OFF by configuration setting

– Multiple clock sources

– 8 selectable time out period from 6ms ~ 3.0sec (depends on clock source)

– WDT can wake up power down/sleep.

– Interrupt or reset selectable on watchdog time-out.

• RTC

– Support software compensation by setting frequency compensate register (FCR)

– Support RTC counter (second, minute, hour) and calendar counter (day, month, year)

– Support Alarm registers (second, minute, hour, day, month, year)

– Selectable 12-hour or 24-hour mode

– Automatic leap year recognition

– Support time tick interrupt

– Support wake up function.

• PWM/Capture

– Built-in up to four 16-bit PWM generators provide eight PWM outputs or four complementary

paired PWM outputs.

– Each PWM generator equipped with one clock source selector, one clock divider, one 8-bit

prescaler and one Dead-Zone generator for complementary paired PWM.

– PWM interrupt synchronous to PWM period.

– Up to eight 16-bit digital Capture timers (shared with PWM timers) provide eight rising/falling

capture inputs.

– Support Capture interrupt

• UART

– Three compatible 16550 UART devices.

– UART ports with flow control (TX, RX, CTS and RTS)

– UART0 with 64-byte FIFO is for high speed

– UART1/2 with 16-byte FIFO for standard device

– Support IrDA (SIR) and LIN function

– Programmable baud-rate generator up to 1/16 system clock

– Support PDMA mode

• SPI

– Up to four sets of SPI device.

– Master up to 20Mbps / Slave up to 10 Mbps.

– Support MICROWIRE/SPI master/slave mode (SSP)

– Full duplex synchronous serial data transfer

– Variable length of transfer data from 1 to 32 bits

– MSB or LSB first data transfer

– 2 slave/device select lines when it is as the master, and 1 slave/device select line when it is as

the slave

– Byte Sleeping mode in 32-bit transmission

– Support PDMA mode

NUC1XX Series Technical Reference Manual

Publication Release Date: June 7, 2010

- 20 - Revision V1.03

• I

– Two sets of I

C device.

– Master/Slave up to 1Mbit/s

– Bidirectional data transfer between masters and slaves

– Multi-master bus (no central master).

– Arbitration between simultaneously transmitting masters without corruption of serial data on

the bus

– Serial clock synchronization allows devices with different bit rates to communicate vian one

serial bus.

– Serial clock synchronization can be used as a handshake mechanism to suspend and resume

serial transfer.

– Programmable clocks allow versatile rate control.

– I2C-bus controllers support multiple address recognition ( two slave address with mask option)

• I

– Interface with external audio CODEC

– Operate as either master or slave mode

– Capable of handling 8, 16, 24 and 32 bit word sizes

– Mono and stereo audio data supported

– I

S and MSB justified data format supported

– Two 8 word FIFO data buffers are provided, one for transmit and one for receive

– Generates interrupt requests when buffer levels cross a programmable boundary

– Support two DMA requests, one for transmit and one for receive

• CAN 2.0

– CAN 2.0B protocol compatible device

– Support 11-bit identifier as well as 29-bit identifier

– Bit rates up to 1Mbits/s

– NRZ bit Coding/ Encoding

– Error Detection & Status Report

 Bit error, Form error, Stuffing error, 15-bit CRC detection, and Acknowledge error

Interrupt

 Each CAN-bus error and Transmission/Receive Done.

– Bit Timing Synchronization

– Acceptance filter extension

– Sleep mode wake up

• ADC

– 12-bit SAR ADC with 800ksps

– Up to 8-ch single-end mode or 4-ch differential mode

– Single scan/single cycle scan/continuous scan

– Each channel with individual result register

– Scan on enabled channels

– Threshold voltage detection

– Conversion start by S/W, external pins

– Support PDMA Mode

• Analog Comparator

– Two analog comparator modules

– External input or internal bandgap voltage selectable at negative node

– Interrupt when compare result change

– Power down wake up

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