AD9235数据手册：高性能ADC规格与特性

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"AD9235是一款高性能的模数转换器，由Analog Devices公司生产。该数据手册提供了关于AD9235芯片的详细技术规格和功能介绍。" AD9235是一款12位高速模拟数字转换器（ADC），设计用于在单一3V电源（2.7V至3.6V）下操作，适用于各种高速信号处理应用。它以低功耗（65 MSPS时为300毫瓦）和高信噪比（SNR）为特点，提供卓越的性能。主要特性包括： 1. **信噪比(SNR)**：在65 MSPS采样速率下，SNR达到70 dBc，这表明AD9235能有效地将模拟信号转换为数字信号，同时保持较高的信号质量。 2. **失真噪声比(SFDR)**：在同一采样速率下，SFDR为85 dBc，这意味着在满量程操作时，非谐波失真和噪声非常低。 3. **低功耗**：在高采样速率下，AD9235仅消耗300毫瓦的功率，这使得它成为能源效率要求高的应用的理想选择。 4. **差分输入**：具备500MHz的带宽，支持差分输入，可以处理高频信号，提高抗干扰能力。 5. **片上参考源和采样保持放大器(SHA)**：集成的参考源和SHA简化了系统设计，减少了外部组件的需求。 6. **差动输入范围**：灵活的模拟输入，最大1Vp-p，适应不同的输入信号条件。 7. **线性度(DNL)**：差动非线性度(DNL)为±0.4 LSB，确保了输出数字序列的精确性。该器件还包括一个11/2位流水线架构，由8个阶段组成，以及一个时钟周期稳定器，以改善时钟偏斜对转换性能的影响。用户可以通过MODE引脚选择不同的工作模式，并通过PDWN引脚控制ADC的电源状态。此外，REFSELECT引脚允许用户选择外部或内部参考电压，而输出缓冲器则确保了稳定的数字输出。 AD9235的封装可能包含保护功能，如OTR（过热关闭），以防止在极端温度条件下操作损坏芯片。该器件的电源和地线（如AVDD和DGND）需要正确连接以确保正常运行。整体而言，AD9235适用于需要高分辨率、高速转换和低功耗的通信、测试与测量、医疗成像等多种应用。

REV. B

AD9235

–6–

PIN CONFIGURATION

28-Lead TSSOP 32-Lead LFCSP

PIN 1

INDICATOR

TOP VIEW

(Not to Scale)

24 VREF

23 SENSE

22 MODE

21 OTR

DNC 1

CLK 2

DNC 3

32 AVDD

20 D11(MSB)

19 D10

18 D9

17 D8

D2 9

D3 10

D4 11

D5 12

D6 13

D7 14

DGND 15

DRVDD 16

PDWN 4

DNC 5

DNC 6

(LSB)D0 7

D1 8

31 AGND

30 VIN–

29 VIN+

28 AGND

27 AVDD

26 REFT

25 REFB

AD9235

PIN FUNCTION DESCRIPTIONS

Pin Number Mnemonic Description

28-Lead 32-Lead

TSSOP LFCSP

121 OTR Out-of-Range Indicator.

222 MODE Data Format and Clock Duty Cycle Stabilizer (DCS) Mode Selection.

323 SENSE Reference Mode Selection.

424 VREF Voltage Reference Input/Output.

525 REFB Differential Reference (–).

626 REFT Differential Reference (+).

7, 12 27, 32 AVDD Analog Power Supply.

8, 11 28, 31 AGND Analog Ground.

929 VIN+ Analog Input Pin (+).

10 30 VIN– Analog Input Pin (–).

13 2 CLK Clock Input Pin.

14 4 PDWN Power-Down Function Selection (Active High).

15–22, 7-14, D0 (LSB)–D11(MSB) Data Output Bits.

25–28 17-20

23 15 DGND Digital Output Ground.

24 16 DRVDD Digital Output Driver Supply. Must be decoupled to DGND with a minimum

0.1 µF capacitor. Recommended decoupling is 0.1 µF in parallel with 10 µF.

1, 3, 5, 6 DNC Do Not Connect.

OTR

MODE

SENSE

VREF

REFB

REFT

AVDD

AGND

VIN+

VIN–

AGND

AVDD

CLK

PDWN

D11 (MSB)

D10

DRVDD

DGND

D0 (LSB)

AD9235

TOP VIEW

(Not to Scale)

REV. B

–7–

AD9235

DEFINITIONS OF SPECIFICATIONS

Analog Bandwidth (Full Power Bandwidth)

The analog input frequency at which the spectral power of the

fundamental frequency (as determined by the FFT analysis) is

reduced by 3 dB.

Aperture Delay (t

)

The delay between the 50% point of the rising edge of the clock

and the instant at which the analog input is sampled.

Aperture Jitter (t

)

The sample-to-sample variation in aperture delay.

Integral Nonlinearity (INL)

The deviation of each individual code from a line drawn from

negative full scale through positive full scale. The point used as

negative full scale occurs 1/2 LSB before the first code transi-

tion. Positive full scale is defined as a level 1 1/2 LSBs beyond

the last code transition. The deviation is measured from the

middle of each particular code to the true straight line.

Differential Nonlinearity (DNL, No Missing Codes)

An ideal ADC exhibits code transitions that are exactly 1 LSB

apart. DNL is the deviation from this ideal value. Guaranteed

no missing codes to 12-bit resolution indicates that all 4096 codes

must be present over all operating ranges.

Offset Error

The major carry transition should occur for an analog value 1/2 LSB

below VIN+ = VIN–. Offset error is defined as the deviation of

the actual transition from that point.

Gain Error

The first code transition should occur at an analog value 1/2

LSB above negative full scale. The last transition should occur

at an analog value 1 1/2 LSB below the positive full scale. Gain

error is the deviation of the actual difference between first and

last code transitions and the ideal difference between first and

last code transitions.

Temperature Drift

The temperature drift for offset error and gain error specifies the

maximum change from the initial (25°C) value to the value at

MIN

or T

MAX

Power Supply Rejection Ratio

The change in full scale from the value with the supply at the

minimum limit to the value with the supply at its maximum

limit.

Total Harmonic Distortion (THD)*

The ratio of the rms sum of the first six harmonic components

to the rms value of the measured input signal.

Signal-to-Noise and Distortion (SINAD)*

The ratio of the rms signal amplitude (set 0.5 dB below full scale)

to the rms value of the sum of all other spectral components below

the Nyquist frequency, including harmonics but excluding dc.

Effective Number of Bits (ENOB)

The effective number of bits for a device for sine wave inputs at

a given input frequency can be calculated directly from its mea-

sured SINAD using the following formula

N SINAD=−

()

176 602..

Signal-to-Noise Ratio (SNR)*

The ratio of the rms signal amplitude (set at 0.5 dB below

full scale) to the rms value of the sum of all other spectral

components below the Nyquist frequency, excluding the first six

harmonics and dc.

Spurious Free Dynamic Range (SFDR)*

The difference in dB between the rms amplitude of the input signal

and the peak spurious signal.

Two-Tone SFDR*

The ratio of the rms value of either input tone to the rms value

of the peak spurious component. The peak spurious component

may or may not be an IMD product.

Clock Pulsewidth and Duty Cycle

Pulsewidth high is the minimum amount of time that the clock

pulse should be left in the Logic 1 state to achieve rated perfor-

mance. Pulsewidth low is the minimum time the clock pulse

should be left in the low state. At a given clock rate, these speci-

fications define an acceptable clock duty cycle.

Minimum Conversion Rate

The clock rate at which the SNR of the lowest analog signal

frequency drops by no more than 3 dB below the guaranteed limit.

Maximum Conversion Rate

The clock rate at which parametric testing is performed.

Output Propagation Delay (t

)

The delay between the clock logic threshold and the time when

all bits are within valid logic levels.

Out-of-Range Recovery Time

The time it takes for the ADC to reacquire the analog input after

a transition from 10% above positive full scale to 10% above

negative full scale, or from 10% below negative full scale to 10%

below positive full scale.

*AC specifications may be reported in dBc (degrades as signal levels are lowered) or in dBFS (always related back to converter full scale).

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