DSP C64X系列技术详解与性能分析

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"该资源是一份关于德州仪器(Texas Instruments, TI)的DSP C64X系列处理器的文档，旨在提供对该系列DSP芯片的全面概述。文档可能包含了技术规格、性能特点以及与C64X家族其他成员的兼容性信息。" TI的DSP C64X系列是高性能的定点数字信号处理器，特别适用于需要复杂计算处理的应用，如通信、音频处理、图像处理等。这一系列处理器以其强大的处理能力著称，能在单一指令周期内执行多个操作，从而实现高效的数据处理。文档中提到的亮点包括： 1. **控制基线**: 指该系列芯片遵循统一的生产与测试标准，确保了产品的质量和一致性。 2. **扩展温度性能**: 支持在−40°C到105°C的宽温范围内工作，适应各种环境条件。 3. **增强的制造源减退支持(DMS)**: 提供持续的技术支持和服务，即使在产品生命周期末期。 4. **增强的产品变更通知**: 可能涉及到芯片设计或功能的更新，确保用户能够及时获取最新信息。 5. **资格认证谱系**: 暗示了这些芯片已经过严格的测试和验证，符合行业标准。 6. **最高性能的定点DSPs**: 提供了不同速度等级的时钟频率，如600、720、850 MHz和1 GHz，以及高达8000 MIPS（每秒百万指令）的处理能力。 7. **软件兼容性**: C64X系列与C62x系列完全软件兼容，降低了迁移成本。 8. **C6414/15/16设备引脚兼容**: 这意味着这些芯片可以在相同的硬件平台上互换使用，提供了设计的灵活性。 9. **VelociTI.2扩展**: 对基础的VelociTI先进超长指令集(VLIW)架构的增强，拥有8个高度独立的功能单元，支持非对齐加载和存储，并有64个32位通用寄存器。 10. **指令打包**: 减少代码大小，提高存储效率。 11. **所有指令有条件执行**: 提高了程序的可控性和效率。 12. **VCP(语音压缩处理器)**: 支持超过8337.95 Kbps的AMR(自适应多速率)编码，适用于语音通信应用，且具有可编程的代码参数。 13. **TCP(通信处理器)**: 能够支持高达102-...的某种通信标准或协议，可能涉及到高速数据传输。这些特性使得C64X系列成为各种高性能信号处理应用的理想选择，如无线通信、视频编码、音频处理、网络基础设施等领域。通过这些详细信息，开发者可以更好地理解和利用这些处理器的强大功能，以构建高效的嵌入式系统。

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   

SGUS056A − MARCH 2005 − REVISED FEBRUARY 2006

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Table 6. L2 Cache Registers (Continued)

HEX ADDRESS RANGE COMMENTSREGISTER NAMEACRONYM

0184 8290 MAR164 Controls EMIFA CE2 range A400 0000 − A4FF FFFF

0184 8294 MAR165 Controls EMIFA CE2 range A500 0000 − A5FF FFFF

0184 8298 MAR166 Controls EMIFA CE2 range A600 0000 − A6FF FFFF

0184 829C MAR167 Controls EMIFA CE2 range A700 0000 − A7FF FFFF

0184 82A0 MAR168 Controls EMIFA CE2 range A800 0000 − A8FF FFFF

0184 82A4 MAR169 Controls EMIFA CE2 range A900 0000 − A9FF FFFF

0184 82A8 MAR170 Controls EMIFA CE2 range AA00 0000 − AAFF FFFF

0184 82AC MAR171 Controls EMIFA CE2 range AB00 0000 − ABFF FFFF

0184 82B0 MAR172 Controls EMIFA CE2 range AC00 0000 − ACFF FFFF

0184 82B4 MAR173 Controls EMIFA CE2 range AD00 0000 − ADFF FFFF

0184 82B8 MAR174 Controls EMIFA CE2 range AE00 0000 − AEFF FFFF

0184 82BC MAR175 Controls EMIFA CE2 range AF00 0000 − AFFF FFFF

0184 82C0 MAR176 Controls EMIFA CE3 range B000 0000 − B0FF FFFF

0184 82C4 MAR177 Controls EMIFA CE3 range B100 0000 − B1FF FFFF

0184 82C8 MAR178 Controls EMIFA CE3 range B200 0000 − B2FF FFFF

0184 82CC MAR179 Controls EMIFA CE3 range B300 0000 − B3FF FFFF

0184 82D0 MAR180 Controls EMIFA CE3 range B400 0000 − B4FF FFFF

0184 82D4 MAR181 Controls EMIFA CE3 range B500 0000 − B5FF FFFF

0184 82D8 MAR182 Controls EMIFA CE3 range B600 0000 − B6FF FFFF

0184 82DC MAR183 Controls EMIFA CE3 range B700 0000 − B7FF FFFF

0184 82E0 MAR184 Controls EMIFA CE3 range B800 0000 − B8FF FFFF

0184 82E4 MAR185 Controls EMIFA CE3 range B900 0000 − B9FF FFFF

0184 82E8 MAR186 Controls EMIFA CE3 range BA00 0000 − BAFF FFFF

0184 82EC MAR187 Controls EMIFA CE3 range BB00 0000 − BBFF FFFF

0184 82F0 MAR188 Controls EMIFA CE3 range BC00 0000 − BCFF FFFF

0184 82F4 MAR189 Controls EMIFA CE3 range BD00 0000 − BDFF FFFF

0184 82F8 MAR190 Controls EMIFA CE3 range BE00 0000 − BEFF FFFF

0184 82FC MAR191 Controls EMIFA CE3 range BF00 0000 − BFFF FFFF

0184 8300 − 0184 83FC

MAR192 to

MAR255

Reserved

0184 8400 − 0187 FFFF − Reserved

peripheral register descriptions (continued)

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   

SGUS056A − MARCH 2005 − REVISED FEBRUARY 2006

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

peripheral register descriptions (continued)

Table 8. EDMA Parameter RAM

†

HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS

01A0 0000 − 01A0 0017 − Parameters for Event 0 (6 words)

01A0 0018 − 01A0 002F − Parameters for Event 1 (6 words)

01A0 0030 − 01A0 0047 − Parameters for Event 2 (6 words)

01A0 0048 − 01A0 005F − Parameters for Event 3 (6 words)

01A0 0060 − 01A0 0077 − Parameters for Event 4 (6 words)

01A0 0078 − 01A0 008F − Parameters for Event 5 (6 words)

01A0 0090 − 01A0 00A7 − Parameters for Event 6 (6 words)

01A0 00A8 − 01A0 00BF − Parameters for Event 7 (6 words)

01A0 00C0 − 01A0 00D7 − Parameters for Event 8 (6 words)

01A0 00D8 − 01A0 00EF − Parameters for Event 9 (6 words)

01A0 00F0 − 01A0 00107 − Parameters for Event 10 (6 words)

01A0 0108 − 01A0 011F − Parameters for Event 11 (6 words)

01A0 0120 − 01A0 0137 − Parameters for Event 12 (6 words)

01A0 0138 − 01A0 014F − Parameters for Event 13 (6 words)

01A0 0150 − 01A0 0167 − Parameters for Event 14 (6 words)

01A0 0168 − 01A0 017F − Parameters for Event 15 (6 words)

01A0 0150 − 01A0 0167 − Parameters for Event 16 (6 words)

01A0 0168 − 01A0 017F − Parameters for Event 17 (6 words)

... ...

01A0 05D0 − 01A0 05E7 − Parameters for Event 62 (6 words)

01A0 05E8 − 01A0 05FF − Parameters for Event 63 (6 words)

01A0 0600 − 01A0 0617 − Reload/link parameters for Event M (6 words)

01A0 0618 − 01A0 062F − Reload/link parameters for Event N (6 words)

... ...

01A0 07E0 − 01A0 07F7 − Reload/link parameters for Event Z (6 words)

01A0 07F8 − 01A0 07FF − Scratch pad area (2 words)

†

The C6416T device has twenty-one parameter sets [six (6) words each] that can be used to reload/link EDMA transfers.

Table 9. Quick DMA (QDMA) and Pseudo Registers

HEX ADDRESS RANGE ACRONYM REGISTER NAME

0200 0000 QOPT QDMA options parameter register

0200 0004 QSRC QDMA source address register

0200 0008 QCNT QDMA frame count register

0200 000C QDST QDMA destination address register

0200 0010 QIDX QDMA index register

0200 0014 − 0200 001C Reserved

0200 0020 QSOPT QDMA pseudo options register

0200 0024 QSSRC QDMA pseudo source address register

0200 0028 QSCNT QDMA pseudo frame count register

0200 002C QSDST QDMA pseudo destination address register

0200 0030 QSIDX QDMA pseudo index register

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   

SGUS056A − MARCH 2005 − REVISED FEBRUARY 2006

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

peripheral register descriptions (continued)

Table 10. Interrupt Selector Registers

HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS

019C 0000 MUXH Interrupt multiplexer high

Selects which interrupts drive CPU

interrupts 10−15 (INT10−INT15)

019C 0004 MUXL Interrupt multiplexer low

Selects which interrupts drive CPU

interrupts 4−9 (INT04−INT09)

019C 0008 EXTPOL External interrupt polarity

Sets the polarity of the external

interrupts (EXT_INT4−EXT_INT7)

019C 000C − 019C 01FF − Reserved

Table 11. McBSP 0 Registers

HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS

018C 0000 DRR0 McBSP0 data receive register via Configuration Bus

The CPU and EDMA controller

can only read this register;

they cannot write to it.

0x3000 0000 − 0x33FF FFFF DRR0 McBSP0 data receive register via Peripheral Bus

018C 0004 DXR0 McBSP0 data transmit register via Configuration Bus

0x3000 0000 − 0x33FF FFFF DXR0 McBSP0 data transmit register via Peripheral Bus

018C 0008 SPCR0 McBSP0 serial port control register

018C 000C RCR0 McBSP0 receive control register

018C 0010 XCR0 McBSP0 transmit control register

018C 0014 SRGR0 McBSP0 sample rate generator register

018C 0018 MCR0 McBSP0 multichannel control register

018C 001C RCERE00 McBSP0 enhanced receive channel enable register 0

018C 0020 XCERE00 McBSP0 enhanced transmit channel enable register 0

018C 0024 PCR0 McBSP0 pin control register

018C 0028 RCERE10 McBSP0 enhanced receive channel enable register 1

018C 002C XCERE10 McBSP0 enhanced transmit channel enable register 1

018C 0030 RCERE20 McBSP0 enhanced receive channel enable register 2

018C 0034 XCERE20 McBSP0 enhanced transmit channel enable register 2

018C 0038 RCERE30 McBSP0 enhanced receive channel enable register 3

018C 003C XCERE30 McBSP0 enhanced transmit channel enable register 3

018C 0040 − 018F FFFF – Reserved

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   

SGUS056A − MARCH 2005 − REVISED FEBRUARY 2006

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

peripheral register descriptions (continued)

Table 12. McBSP 1 Registers

HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS

0190 0000 DRR1 McBSP1 data receive register via Configuration Bus

The CPU and EDMA controller

can only read this register;

they cannot write to it.

0x3400 0000 − 0x37FF FFFF DRR1 McBSP1 data receive register via Peripheral Bus

0190 0004 DXR1 McBSP1 data transmit register via Configuration Bus

0x3400 0000 − 0x37FF FFFF DXR1 McBSP1 data transmit register via Peripheral Bus

0190 0008 SPCR1 McBSP1 serial port control register

0190 000C RCR1 McBSP1 receive control register

0190 0010 XCR1 McBSP1 transmit control register

0190 0014 SRGR1 McBSP1 sample rate generator register

0190 0018 MCR1 McBSP1 multichannel control register

0190 001C RCERE01 McBSP1 enhanced receive channel enable register 0

0190 0020 XCERE01 McBSP1 enhanced transmit channel enable register 0

0190 0024 PCR1 McBSP1 pin control register

0190 0028 RCERE11 McBSP1 enhanced receive channel enable register 1

0190 002C XCERE11 McBSP1 enhanced transmit channel enable register 1

0190 0030 RCERE21 McBSP1 enhanced receive channel enable register 2

0190 0034 XCERE21 McBSP1 enhanced transmit channel enable register 2

0190 0038 RCERE31 McBSP1 enhanced receive channel enable register 3

0190 003C XCERE31 McBSP1 enhanced transmit channel enable register 3

0190 0040 − 0193 FFFF – Reserved

Table 13. McBSP 2 Registers

HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS

01A4 0000 DRR2 McBSP2 data receive register via Configuration Bus

The CPU and EDMA controller

can only read this register;

they cannot write to it.

0x3800 0000 − 0x3BFF FFFF DRR2 McBSP2 data receive register via Peripheral Bus

01A4 0004 DXR2 McBSP2 data transmit register via Configuration Bus

0x3800 0000 − 0x3BFF FFFF DXR2 McBSP2 data transmit register via Peripheral Bus

01A4 0008 SPCR2 McBSP2 serial port control register

01A4 000C RCR2 McBSP2 receive control register

01A4 0010 XCR2 McBSP2 transmit control register

01A4 0014 SRGR2 McBSP2 sample rate generator register

01A4 0018 MCR2 McBSP2 multichannel control register

01A4 001C RCERE02 McBSP2 enhanced receive channel enable register 0

01A4 0020 XCERE02 McBSP2 enhanced transmit channel enable register 0

01A4 0024 PCR2 McBSP2 pin control register

01A4 0028 RCERE12 McBSP2 enhanced receive channel enable register 1

01A4 002C XCERE12 McBSP2 enhanced transmit channel enable register 1

01A4 0030 RCERE22 McBSP2 enhanced receive channel enable register 2

01A4 0034 XCERE22 McBSP2 enhanced transmit channel enable register 2

01A4 0038 RCERE32 McBSP2 enhanced receive channel enable register 3

01A4 003C XCERE32 McBSP2 enhanced transmit channel enable register 3

01A4 0040 − 01A7 FFFF – Reserved

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