TM4C123GH6PM微控制器开发手册

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"TM4C123GH6PM是一款由德州仪器（Texas Instruments）推出的微控制器，属于Tiva™系列。这款芯片的手册包含了详细的技术规格、功能描述、引脚配置、电气特性以及应用信息。" TM4C123GH6PM芯片是基于ARM Cortex-M4内核的微控制器，其主要特点包括高性能、低功耗和丰富的外设接口。Cortex-M4内核支持ARM的 Thumb-2指令集，提供了高效的代码执行能力和浮点运算单元，适合于需要实时处理和计算密集型任务的应用。该芯片的主要特性包括： 1. **高性能CPU核心**：内置32位ARM Cortex-M4F处理器，具备硬件乘法器和浮点单元（FPU），可以执行复杂的数学运算。 2. **内存配置**：通常包含闪存和SRAM，用于存储程序代码和工作数据。具体容量需参考完整手册。 3. **外设接口**：提供多种通信接口，如UART、SPI、I2C、CAN、USB等，便于与外部设备交互。 4. **模拟功能**：包括ADC（模数转换器）、DAC（数模转换器）、比较器、PWM（脉宽调制）等，适用于信号处理和控制应用。 5. **时钟系统**：灵活的时钟源管理，可以根据应用需求选择不同的时钟源和频率。 6. **电源管理**：具有低功耗模式，可优化在不同应用场景下的功耗。 7. **中断系统**：支持多个中断源，便于实时响应事件。 8. **安全特性**：可能包括加密硬件、安全引导等，增强系统安全性。 9. **封装形式**：TM4C123GH6PM可能采用不同的封装形式，如LQFP封装，提供多引脚接口。开发TM4C123GH6PM时，开发者可以利用TivaWare软件库，这是一个由德州仪器提供的全面的固件库，包含了驱动程序、示例代码和工具，以简化开发流程。此外，TI还提供了相应的开发工具，如Code Composer Studio集成开发环境，支持调试和编程功能。在使用此芯片进行设计时，工程师应参照官方提供的数据表，确保产品符合TI的标准保修条款，并注意芯片不一定会测试所有参数。对于关键应用，需仔细评估TI半导体产品的适用性和风险，因为数据表的末尾通常会包含关于产品可用性、标准保修以及在关键应用中使用TI半导体产品的免责声明。同时，可以通过TI的官方网站获取最新的技术支持和产品信息。

Table 16-4. Inter-Integrated Circuit (I

C) Interface Register Map ........................................... 1017

Table 16-5. Write Field Decoding for I2CMCS[3:0] Field ....................................................... 1023

Table 17-1. Controller Area Network Signals (64LQFP) ........................................................ 1050

Table 17-2. Message Object Configurations ........................................................................ 1055

Table 17-3. CAN Protocol Ranges ...................................................................................... 1063

Table 17-4. CANBIT Register Values .................................................................................. 1063

Table 17-5. CAN Register Map ........................................................................................... 1067

Table 18-1. USB Signals (64LQFP) .................................................................................... 1101

Table 18-2. Remainder (MAXLOAD/4) ................................................................................ 1112

Table 18-3. Actual Bytes Read ........................................................................................... 1112

Table 18-4. Packet Sizes That Clear RXRDY ...................................................................... 1113

Table 18-5. Universal Serial Bus (USB) Controller Register Map ........................................... 1114

Table 19-1. Analog Comparators Signals (64LQFP) ............................................................. 1216

Table 19-2. Internal Reference Voltage and ACREFCTL Field Values ................................... 1218

Table 19-3. Analog Comparator Voltage Reference Characteristics, V

DDA

= 3.3V, EN= 1, and

RNG = 0 .......................................................................................................... 1219

Table 19-4. Analog Comparator Voltage Reference Characteristics, V

DDA

= 3.3V, EN= 1, and

RNG = 1 .......................................................................................................... 1219

Table 19-5. Analog Comparators Register Map ................................................................... 1220

Table 20-1. PWM Signals (64LQFP) ................................................................................... 1233

Table 20-2. PWM Register Map .......................................................................................... 1240

Table 21-1. QEI Signals (64LQFP) ...................................................................................... 1307

Table 21-2. QEI Register Map ............................................................................................ 1311

Table 23-1. GPIO Pins With Special Considerations ............................................................ 1329

Table 23-2. Signals by Pin Number ..................................................................................... 1330

Table 23-3. Signals by Signal Name ................................................................................... 1337

Table 23-4. Signals by Function, Except for GPIO ............................................................... 1344

Table 23-5. GPIO Pins and Alternate Functions ................................................................... 1351

Table 23-6. Possible Pin Assignments for Alternate Functions .............................................. 1353

Table 23-7. Connections for Unused Signals (64-Pin LQFP) ................................................. 1356

Table 24-1. Absolute Maximum Ratings .............................................................................. 1358

Table 24-2. ESD Absolute Maximum Ratings ...................................................................... 1358

Table 24-3. Temperature Characteristics ............................................................................. 1359

Table 24-4. Thermal Characteristics ................................................................................... 1359

Table 24-5. Recommended DC Operating Conditions .......................................................... 1360

Table 24-6. Recommended GPIO Pad Operating Conditions ................................................ 1360

Table 24-7. GPIO Current Restrictions ................................................................................ 1360

Table 24-8. GPIO Package Side Assignments ..................................................................... 1361

Table 24-9. JTAG Characteristics ....................................................................................... 1363

Table 24-10. Power-On and Brown-Out Levels ...................................................................... 1365

Table 24-11. Reset Characteristics ....................................................................................... 1370

Table 24-12. LDO Regulator Characteristics ......................................................................... 1373

Table 24-13. Phase Locked Loop (PLL) Characteristics ......................................................... 1374

Table 24-14. Actual PLL Frequency ...................................................................................... 1374

Table 24-15. PIOSC Clock Characteristics ............................................................................ 1375

Table 24-16. Low-Frequency internal Oscillator Characteristics .............................................. 1375

Table 24-17. Hibernation Oscillator Input Characteristics ........................................................ 1375

Table 24-18. Main Oscillator Input Characteristics ................................................................. 1376

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Table 24-19. Crystal Parameters .......................................................................................... 1378

Table 24-20. Supported MOSC Crystal Frequencies .............................................................. 1379

Table 24-21. System Clock Characteristics with ADC Operation ............................................. 1380

Table 24-22. System Clock Characteristics with USB Operation ............................................. 1380

Table 24-23. Sleep Modes AC Characteristics ....................................................................... 1381

Table 24-24. Time to Wake with Respect to Low-Power Modes .............................................. 1381

Table 24-25. Hibernation Module Battery Characteristics ....................................................... 1383

Table 24-26. Hibernation Module AC Characteristics ............................................................. 1383

Table 24-27. Flash Memory Characteristics ........................................................................... 1384

Table 24-28. EEPROM Characteristics ................................................................................. 1384

Table 24-29. GPIO Module Characteristics ............................................................................ 1385

Table 24-30. Pad Voltage/Current Characteristics for Fail-Safe Pins ....................................... 1386

Table 24-31. Fail-Safe GPIOs that Require an External Pull-up .............................................. 1387

Table 24-32. Non-Fail-Safe I/O Pad Voltage/Current Characteristics ....................................... 1387

Table 24-33. ADC Electrical Characteristics .......................................................................... 1389

Table 24-34. SSI Characteristics .......................................................................................... 1392

Table 24-35. I

C Characteristics ........................................................................................... 1395

Table 24-36. Analog Comparator Characteristics ................................................................... 1397

Table 24-37. Analog Comparator Voltage Reference Characteristics ...................................... 1397

Table 24-38. Analog Comparator Voltage Reference Characteristics, V

DDA

= 3.3V, EN= 1, and

RNG = 0 .......................................................................................................... 1397

Table 24-39. Analog Comparator Voltage Reference Characteristics, V

DDA

= 3.3V, EN= 1, and

RNG = 1 .......................................................................................................... 1398

Table 24-40. PWM Timing Characteristics ............................................................................. 1398

Table 24-41. Current Consumption ....................................................................................... 1399

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Tiva

™

TM4C123GH6PM Microcontroller

List of Registers

The Cortex-M4F Processor ........................................................................................................... 69

Register 1: Cortex General-Purpose Register 0 (R0) ........................................................................... 77

Register 2: Cortex General-Purpose Register 1 (R1) ........................................................................... 77

Register 3: Cortex General-Purpose Register 2 (R2) ........................................................................... 77

Register 4: Cortex General-Purpose Register 3 (R3) ........................................................................... 77

Register 5: Cortex General-Purpose Register 4 (R4) ........................................................................... 77

Register 6: Cortex General-Purpose Register 5 (R5) ........................................................................... 77

Register 7: Cortex General-Purpose Register 6 (R6) ........................................................................... 77

Register 8: Cortex General-Purpose Register 7 (R7) ........................................................................... 77

Register 9: Cortex General-Purpose Register 8 (R8) ........................................................................... 77

Register 10: Cortex General-Purpose Register 9 (R9) ........................................................................... 77

Register 11: Cortex General-Purpose Register 10 (R10) ....................................................................... 77

Register 12: Cortex General-Purpose Register 11 (R11) ........................................................................ 77

Register 13: Cortex General-Purpose Register 12 (R12) ....................................................................... 77

Register 14: Stack Pointer (SP) ........................................................................................................... 78

Register 15: Link Register (LR) ............................................................................................................ 79

Register 16: Program Counter (PC) ..................................................................................................... 80

Register 17: Program Status Register (PSR) ........................................................................................ 81

Register 18: Priority Mask Register (PRIMASK) .................................................................................... 85

Register 19: Fault Mask Register (FAULTMASK) .................................................................................. 86

Register 20: Base Priority Mask Register (BASEPRI) ............................................................................ 87

Register 21: Control Register (CONTROL) ........................................................................................... 88

Register 22: Floating-Point Status Control (FPSC) ................................................................................ 90

Cortex-M4 Peripherals ................................................................................................................. 122

Register 4: Interrupt 0-31 Set Enable (EN0), offset 0x100 .................................................................. 142

Register 5: Interrupt 32-63 Set Enable (EN1), offset 0x104 ................................................................ 142

Register 6: Interrupt 64-95 Set Enable (EN2), offset 0x108 ................................................................ 142

Register 7: Interrupt 96-127 Set Enable (EN3), offset 0x10C ............................................................. 142

Register 8: Interrupt 128-138 Set Enable (EN4), offset 0x110 ............................................................ 143

Register 9: Interrupt 0-31 Clear Enable (DIS0), offset 0x180 .............................................................. 144

Register 10: Interrupt 32-63 Clear Enable (DIS1), offset 0x184 ............................................................ 144

Register 11: Interrupt 64-95 Clear Enable (DIS2), offset 0x188 ............................................................ 144

Register 12: Interrupt 96-127 Clear Enable (DIS3), offset 0x18C .......................................................... 144

Register 13: Interrupt 128-138 Clear Enable (DIS4), offset 0x190 ........................................................ 145

Register 14: Interrupt 0-31 Set Pending (PEND0), offset 0x200 ........................................................... 146

Register 15: Interrupt 32-63 Set Pending (PEND1), offset 0x204 ......................................................... 146

Register 16: Interrupt 64-95 Set Pending (PEND2), offset 0x208 ......................................................... 146

Register 17: Interrupt 96-127 Set Pending (PEND3), offset 0x20C ....................................................... 146

Register 18: Interrupt 128-138 Set Pending (PEND4), offset 0x210 ...................................................... 147

Register 19: Interrupt 0-31 Clear Pending (UNPEND0), offset 0x280 ................................................... 148

Register 20: Interrupt 32-63 Clear Pending (UNPEND1), offset 0x284 .................................................. 148

Register 21: Interrupt 64-95 Clear Pending (UNPEND2), offset 0x288 .................................................. 148

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Register 24: Interrupt 0-31 Active Bit (ACTIVE0), offset 0x300 ............................................................. 150

Register 25: Interrupt 32-63 Active Bit (ACTIVE1), offset 0x304 ........................................................... 150

Register 26: Interrupt 64-95 Active Bit (ACTIVE2), offset 0x308 ........................................................... 150

Register 27: Interrupt 96-127 Active Bit (ACTIVE3), offset 0x30C ........................................................ 150

Register 28: Interrupt 128-138 Active Bit (ACTIVE4), offset 0x310 ....................................................... 151

Register 29: Interrupt 0-3 Priority (PRI0), offset 0x400 ......................................................................... 152

Register 30: Interrupt 4-7 Priority (PRI1), offset 0x404 ......................................................................... 152

Register 31: Interrupt 8-11 Priority (PRI2), offset 0x408 ....................................................................... 152

Register 32: Interrupt 12-15 Priority (PRI3), offset 0x40C .................................................................... 152

Register 33: Interrupt 16-19 Priority (PRI4), offset 0x410 ..................................................................... 152

Register 34: Interrupt 20-23 Priority (PRI5), offset 0x414 ..................................................................... 152

Register 35: Interrupt 24-27 Priority (PRI6), offset 0x418 ..................................................................... 152

Register 36: Interrupt 28-31 Priority (PRI7), offset 0x41C .................................................................... 152

Register 37: Interrupt 32-35 Priority (PRI8), offset 0x420 ..................................................................... 152

Register 38: Interrupt 36-39 Priority (PRI9), offset 0x424 ..................................................................... 152

Register 39: Interrupt 40-43 Priority (PRI10), offset 0x428 ................................................................... 152

Register 40: Interrupt 44-47 Priority (PRI11), offset 0x42C ................................................................... 152

Register 41: Interrupt 48-51 Priority (PRI12), offset 0x430 ................................................................... 152

Register 42: Interrupt 52-55 Priority (PRI13), offset 0x434 ................................................................... 152

Register 43: Interrupt 56-59 Priority (PRI14), offset 0x438 ................................................................... 152

Register 44: Interrupt 60-63 Priority (PRI15), offset 0x43C .................................................................. 152

Register 45: Interrupt 64-67 Priority (PRI16), offset 0x440 ................................................................... 154

Register 46: Interrupt 68-71 Priority (PRI17), offset 0x444 ................................................................... 154

Register 47: Interrupt 72-75 Priority (PRI18), offset 0x448 ................................................................... 154

Register 48: Interrupt 76-79 Priority (PRI19), offset 0x44C .................................................................. 154

Register 49: Interrupt 80-83 Priority (PRI20), offset 0x450 ................................................................... 154

Register 50: Interrupt 84-87 Priority (PRI21), offset 0x454 ................................................................... 154

Register 51: Interrupt 88-91 Priority (PRI22), offset 0x458 ................................................................... 154

Register 52: Interrupt 92-95 Priority (PRI23), offset 0x45C .................................................................. 154

Register 53: Interrupt 96-99 Priority (PRI24), offset 0x460 ................................................................... 154

Register 54: Interrupt 100-103 Priority (PRI25), offset 0x464 ............................................................... 154

Register 55: Interrupt 104-107 Priority (PRI26), offset 0x468 ............................................................... 154

Register 56: Interrupt 108-111 Priority (PRI27), offset 0x46C ............................................................... 154

Register 57: Interrupt 112-115 Priority (PRI28), offset 0x470 ................................................................ 154

Register 58: Interrupt 116-119 Priority (PRI29), offset 0x474 ................................................................ 154

Register 59: Interrupt 120-123 Priority (PRI30), offset 0x478 ............................................................... 154

Register 60: Interrupt 124-127 Priority (PRI31), offset 0x47C ............................................................... 154

Register 61: Interrupt 128-131 Priority (PRI32), offset 0x480 ............................................................... 154

Register 62: Interrupt 132-135 Priority (PRI33), offset 0x484 ............................................................... 154

Register 63: Interrupt 136-138 Priority (PRI34), offset 0x488 ............................................................... 154

Register 64: Software Trigger Interrupt (SWTRIG), offset 0xF00 .......................................................... 156

Register 65: Auxiliary Control (ACTLR), offset 0x008 .......................................................................... 157

Register 66: CPU ID Base (CPUID), offset 0xD00 ............................................................................... 159

Register 67: Interrupt Control and State (INTCTRL), offset 0xD04 ........................................................ 160

Register 68: Vector Table Offset (VTABLE), offset 0xD08 .................................................................... 163

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Tiva

™

TM4C123GH6PM Microcontroller

Register 70: System Control (SYSCTRL), offset 0xD10 ....................................................................... 166

Register 71: Configuration and Control (CFGCTRL), offset 0xD14 ....................................................... 168

Register 72: System Handler Priority 1 (SYSPRI1), offset 0xD18 ......................................................... 170

Register 73: System Handler Priority 2 (SYSPRI2), offset 0xD1C ........................................................ 171

Register 74: System Handler Priority 3 (SYSPRI3), offset 0xD20 ......................................................... 172

Register 76: Configurable Fault Status (FAULTSTAT), offset 0xD28 ..................................................... 177

Register 77: Hard Fault Status (HFAULTSTAT), offset 0xD2C .............................................................. 183

Register 79: Bus Fault Address (FAULTADDR), offset 0xD38 .............................................................. 185

Register 80: MPU Type (MPUTYPE), offset 0xD90 ............................................................................. 186

Register 81: MPU Control (MPUCTRL), offset 0xD94 .......................................................................... 187

Register 91: Coprocessor Access Control (CPAC), offset 0xD88 .......................................................... 195

Register 92: Floating-Point Context Control (FPCC), offset 0xF34 ........................................................ 196

Register 93: Floating-Point Context Address (FPCA), offset 0xF38 ...................................................... 198

System Control ............................................................................................................................ 212

Register 1: Device Identification 0 (DID0), offset 0x000 ..................................................................... 238

Register 2: Device Identification 1 (DID1), offset 0x004 ..................................................................... 240

Register 4: Raw Interrupt Status (RIS), offset 0x050 .......................................................................... 244

Register 5: Interrupt Mask Control (IMC), offset 0x054 ...................................................................... 247

Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................. 249

Register 7: Reset Cause (RESC), offset 0x05C ................................................................................ 252

Register 8: Run-Mode Clock Configuration (RCC), offset 0x060 ......................................................... 254

Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070 .................................................... 260

Register 11: Main Oscillator Control (MOSCCTL), offset 0x07C ........................................................... 263

Register 13: System Properties (SYSPROP), offset 0x14C .................................................................. 266

Register 16: PLL Frequency 0 (PLLFREQ0), offset 0x160 ................................................................... 271

Register 17: PLL Frequency 1 (PLLFREQ1), offset 0x164 ................................................................... 272

Register 18: PLL Status (PLLSTAT), offset 0x168 ............................................................................... 273

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