MP2975：数字多相控制器支持软件动态调压，优化VR13.HC平台供电

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MPS MP2975是一款专为VR13.HC平台和基于AVS Bus的CPU核心设计的双环数字多相控制器，它在嵌入式系统中扮演着关键角色，特别是在电源管理方面。这款芯片的独特之处在于其软件动态调压能力，允许用户通过编程接口如PMBus/I2C进行设备配置和故障参数监控，从而实现对电源系统的灵活性和定制化。该芯片的核心功能包括：首先，作为多相电源解决方案的一部分，它与MPS和多家厂商的DrMOS产品配合，能够提供高效能的电源供应，减少外部组件的需求，简化系统设计。MP2975支持多达8个PWM通道，可灵活配置，最高可以实现8相电源控制（针对轨1）和4相电源控制（针对轨2），确保了电源性能的多样性。 MP2975的内部集成非易失性存储器(NVM)技术，使得设备的配置信息能够被安全存储并在系统启动时自动恢复，无需外部存储器干预。这大大提升了系统的可靠性，并降低了维护成本。同时，通过CS输出接口，MP2975能够实时监测和报告DrMOS产品的输出电流，帮助用户实时掌握系统运行状态，进行有效的故障诊断和性能优化。设计上，MP2975采用了独特的数字多相控制架构，这使得它在高精度、低噪声以及快速响应方面具有优势，特别适合对电源效率和稳定性有极高要求的应用场景，如高性能服务器、数据中心服务器或者移动设备中的高性能处理器供电。 MPS MP2975是一款集成了高级电源管理和灵活配置能力的嵌入式芯片，它的出现推动了电源管理技术的发展，为用户提供了一个强大且易于使用的平台，显著提升了电子设备的性能和能效。对于在使用Loongson处理器或者其他需要精确电源控制的项目中，MP2975无疑是一个重要的选择。

MP2975 –DUAL LOOP DIGITAL PWM CONTROLLER FOR VR13.HC/AVSBUS

PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE

MP2975 Rev. 0.4 www.MonolithicPower.com 16

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Where

OUT

is the real time output voltage, in V;

is the input voltage, in V;

is the switching frequency set by PMBus,

in Hz.

Voltage Reference

The MP2975 has 9-bit VID DAC which provides

the reference voltage (V

REF

) for the individual

output.

When VID = 0, the V

REF

is 0V as the VR is at

power off state.

When VID > 0, Equation (2) shows the

relationship between V

REF

and VID value in

decimal:



REF RS

VID OFFSET VID STEP mV

V(V) G

1000





(2)

Where,

VID is the commanded voltage identification

value from SVID, PMBus, AVSBus interface or

PVID control, in decimal.

OFFSET is an offset value. OFFSET = 29 when

Intel IMVP9 10mV VID table is selected via

registers 0Dh/1Dh @ page2 (respectively for rail1

and rail2). For others, OFFSET = 49.

VID_STEP is either 5mV or 10mV, determined by

registers 0Dh/1Dh @ page2 (respectively for rail1

and rail2).

is the gain of remote sense amplifier. The

value is 1 with unit gain and 0.5 with half gain

which is determined by bit [11] in register

VOUT_SENSE_SET (29h).

In MP2975, the VID is a 9-bit value. It can be

from SVID interface, AVSBus interface, PMBus

interface or PVID control. The VID control starts

with VID mode selection. Figure 3 shows the VID

control related commands.

Figure 3: VID Control Related Commands

MP2975 –DUAL LOOP DIGITAL PWM CONTROLLER FOR VR13.HC/AVSBUS

PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE

MP2975 Rev. 0.4 www.MonolithicPower.com 17

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The register listed below shows the VID mode

selection bits and related registers:

 PMBUS_EN: MFR_VR_CONFIG2 (5Eh, bit

[9])

 PVID_EN: MFR_VR_CONFIG2 (5Eh, bit [11])

 AVSBUS_EN: OPERATION (01h)

After the VID modes selection, the commanded

voltage developed is compared with the output

voltage limits set by the VOUT_MAX (24h) and

VOUT_MIN (2Bh) commands. If the calculated

voltage command creates an output voltage

higher than the VOUT_MAX value or less than

the VOUT_MIN value, the PMBus device limits

the command voltage to VOUT_MAX or

VOUT_MIN value. And the PMBus Alert# pin can

be asserted as warning to the master.

After the VID limitation, the value from the

VOUT_OFFSET (1Eh @ page2) is added to the

VID. The VOUT_OFFSET register is in two’s

complement format with 1-VID step/LSB. It can

range from -0.64V to +0.635V with 5mV VID

table and -1.28V to +1.27V with 10mV VID table.

It allows the user to adjust target VID to achieve

over-clocking operation. After VOUT_OFFSET

setting, the final VID is formed. A unit gain or half

gain is used to the calculated final input value

into VID DAC. The VID DAC generates the final

reference voltage, which compares with the

sensed output voltage to adjust the duty cycle of

the PWM.

Output Voltage Setting

In Figure 4, the voltage at the load is sensed with

the differential voltage sense amplifier. This type

of sensing provides better load regulation. The

remote sense amplifier can be programmed with

unity gain or half gain with PMBus command

VOUT_SENSE_SET (29h).

The registers 07h/17h @ page2 can add voltage

trimming value respectively on rail1 and rail2, so

as to fine tune the output voltage. They are

0.5mV/LSB with remote sense unit gain, and

0.8mV/LSB with remote sense half gain. This is

used to fine tune the output voltage which can

either add to or subtract an offset from the

remote sensed output voltage. This can adjust

the output voltage to get better VOUT accuracy

for end user’s system.

After voltage trim, the MP2975 senses the

voltage either on VDIFF or VFB with ADC to do

DC voltage calibration, thus provides high

accuracy voltage regulation. The ADC sense also

provides unit gain or half gain to make sure the

voltage is within ADC sensing range.

Table 1 shows the voltage supporting range for

different VID steps and voltage sensing gains.

Table 1: Voltage Support Range

External

VOUT

Divider

VID Table

Gain

VDIFF/VFB

ADC Gain

VOUT

Range

N 5mV 1 1 0~1.25V

N 5mV 0.5 1 0~2.5V

N 10mV 1 1 0~1.6V

N 10mV 1 0.5 0~2.2V

N 10mV 0.5 1 0~3V

Y 5mV/10mV 1 1 >3V

In non-Intel application with V

OUT

> 3V, an

external resistive divider is required from VOUT

to VORTN and tapped to VOSEN as shown in

Figure 4. Set the resistive dividing ratio into

MP2975 with register VOUT_SENSE_SET (29h).

Figure 4: DC Loop gain selection

Active Voltage Positioning (AVP)

The MP2975 supports active voltage positioning

(AVP). With this function, output voltage drops

gradually as the load current increasing. It is also

known as load line. Equation (3) shows the

relationship of output voltage and load current.

MP2975 –DUAL LOOP DIGITAL PWM CONTROLLER FOR VR13.HC/AVSBUS

PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE

MP2975 Rev. 0.4 www.MonolithicPower.com 18

1/2/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

OUT @IOUT OUT @NO LOAD OUT LL

VV IR

(3)

Where,

is the load line resistor.

The MP2975 provides PMBus programmable

load line which is calculated in equation (4).



LL CS DROOP

IDROOP_GAIN_SET 1

RKR

256 G

(4)

Where,

is the current sense gain of Intelli-Phase, in

A/A.

IDROOP_GAIN_SET is a decimal value ranges

from 0-256. When set IDROOP_GAIN_SET = 0,

AVP function is disabled.

DROOP

is an internal resistor across VFB and

VDIFF, in Ω.

Both IDROOP_GAIN_SET and R

DROOP

are set by

registers 06h/16h @ page2.

is the remote sense gain. It can be half or

unit gain.

For the no load line VR application, the MP2975

provides AC-DROOP function to increase the

phase margin of the loop regulation. The AC-

DROOP function injects the AC component of the

total inductor current to the R

DROOP

, so as to

introduce the current signal to the loop regulation.

Enable AC-DROOP function via registers

01h/11h @ page2. The AC-DROOP related

parameters can be programmed with PMBus

registers 06h/16h @ page2. Refer to Register

Map for more information.

Boot Up Voltage Set

The MP2975 sets the boot up voltage by

registers 0Dh/1Dh @ page2 respectively for rail1

and rail2.

In SVID control mode and PMBus override

control mode, the boot up slew rate can be set to

either "slow slew rate" or "Vout transition slew

rate". In AVSBUS control mode, the boot up slew

rate is always "slow slew rate".

"Slow slew rate" is proportional to "fast slew rate".

The proportion is determined by bit[11:8] of

registers 01h/11h @ page2, as Table 2 shows:

Table 2: Slow Slew Rate

bit [11:8] of 01h/11h @ page2 slow slew rate

4’b1xxx FAST_SR/16

4’b01xx FAST_SR/8

4’b001x and 4’b0000 FAST_SR/4

4’b0001 FAST_SR/2

"Fast slew rate" is determined by Equation (5):







VID _ STEP mV

FAST _ SR

SLEW _FAST _ CNT 0.05 s







(5)

Where,

VID_STEP can be set to 5mV or 10mV;

SLEW_FAST_CNT ranges from 1~63 and is

determined by bit[5:0] of registers 01/11h @

page2.

"Vout transition slew rate" is determined by

Equation (6):













VID _ STEP mV

TRANS _ SR

VOUT _ TRANS _ CNT 0.1 s

(6)

Where,

VID_STEP can be either 5mV or 10mV;

VOUT_TRANS_CNT is the decimal value in

VOUT_TRANSITION_RATE (27h), bit [8:0],

which ranges from 1~511.

MP2975 –DUAL LOOP DIGITAL PWM CONTROLLER FOR VR13.HC/AVSBUS

PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE

MP2975 Rev. 0.4 www.MonolithicPower.com 19

1/2/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

PVID Mode

The MP2975 supports 3-bit PVID mode to control

OUT

by setting the PVID_EN bit in register 5Eh.

The PVID mode pins (PVID1, PVID2 and PVID3)

are muxed from SCLK, SDIO, and ALT#. In PVID

mode, SVID and AVSBUS communication are

disabled.

When any of the PVID pins toggle, the internal

VID value starts to slew to new target VID.

There are 8 sets of PVID voltages with different

combinations of High/Low logic on PVID1, PVID2

and PVID3. Registers BAh ~ C1h @ page1 with

target voltage values should be pre-programmed

corresponding to these logic as Table 3 shows.

Table 3: Set PVID voltage by PVID Pins

PVID

Rail1

PVID

Rail2

PVID1

(Pin17)

PVID2

(Pin18)

PVID3

(Pin19)

BAh[7:0] BEh[7:0] L L L

BAh[15:8] BEh[15:8] L L H

BBh[7:0] BFh[7:0] L H L

BBh[15:8] BFh[15:8] L H H

BCh[7:0] C0h[7:0] H L L

BCh[15:8] C0h[15:8] H L H

BDh[7:0] C1h[7:0] H H L

BDh[15:8] C1h[15:8] H H H

AVSBUS mode

The MP2975 supports the AVSBUS control mode.

In AVSBUS mode, the communication signals

AVS_CLK and AVS_MOSI are muxed from the

SCLK and SDIO as input pins. User needs to

configure the AVS_MISO pin according to the

electrical voltage level of AVSBus supply, for the

≤1.8V AVSBus supply application, the

AVS_MISO pin is muxed from ALT# pin; for the

1.8V~3.3V AVSBus supply application, the

AVS_MISO is muxed from VRHOT# pin as

AVS_MISO_HV. The AVS_MISO and

AVS_MISO_HV pin is open-drain so it is required

to add pull up resistor to the system AVSBus

supply.

MP2975 supports all the AVSBus protocol

specified commands:

Voltage Read/Write;

Vout Transition Rate Read/Write;

Current Read;

Temperature Read;

Voltage Reset;

Power Mode Read/Write;

AVSBus Status Read/Write;

AVSBus Version Read;

MP2975 supports slave interrupt function.

In the AVSBUS mode, the SVID communication

is disabled. The AVSBus address setting is same

as the SVID address with register

MFR_ADDR_SVID_AVSBUS (05h @ page2).

SVID Interface

To support multiple VR devices on same SVID

bus, the register MFR_ADDR_SVID_AVSBUS

(05h @ page2) is used to program the SVID

address.

The SVID address is a 4 bit code. There are 14

addresses for up to 14 voltage regulator

controllers or voltage rails. The final address 0Eh

and 0Fh are reserved “All Call” addresses and all

the VR controllers will respond to them. User can

program the bit[10:9] in 05h @ page2 to select

0Eh and/or 0Fh as the “All Call” addresses.

The SVID address of Rail1 and Rail2 are set by

MFR_ADDR_SVID_AVSBUS (05h @ page2).

Refer to Register Map for more details.

If Rail2 doesn’t need SVID address, user can set

the Rail2 to reject all the SVID command from

the processor via bit[13] of the register

MFR_VR_MULTI_CONFIG_R2 (1Dh @ page2).

MP2975 –DUAL LOOP DIGITAL PWM CONTROLLER FOR VR13.HC/AVSBUS

PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE

MP2975 Rev. 0.4 www.MonolithicPower.com 20

1/2/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

Dynamic Voltage Identification (DVID)

The MP2975 supports dynamical output voltage

transition by changing VID code with the PMBus

interface, AVSBUS interface, SVID interface, or

PVID pins toggling.

At the PMBus override control mode and PVID

control mode, the DVID slew rate is set to "Vout

transition slew rate" determined by Equation (6).

At the SVID control mode, the DVID slew rate is

determined by the SetVID command. The slew

rate of SetVID_Fast command is shown as

Equation (5); the slew rate of SetVID_Slow

command is shown in Table 2; the slew rate of

SetVID_Decay command can be set to "slow

slew rate" or free mode in which all PWMs turn to

tri-state and the Vout slew rate is determined by

the C

OUT

value and the load current. Refer to bit[9]

of register MFR_VR_CONFIG1 (68h) for detail.

At the AVSBUS control mode, the DVID slew rate

is determined by the Vout Transition Rate Write

command which is integer with 1LSB = 1mV/µs.

In one Vout Transition Rate command, the rise

slew rate is sent first, followed by the fall slew

rate. The initial rise and fall slew rate is

determined by VOUT_TRANSITION_RATE (27h)

as shown in Equation (7).





100 mV / s

AVS _ SR _INI

VOUT _ TRANS _ CNT





(7)

Where, VOUT_TRANS_CNT is the decimal value

in VOUT_TRANSITION_RATE (27h), bit [8:0],

which ranges from 1~511.

During a VID transient, the MP2975 forces the

VR into full phase CCM mode regardless the

power state setting. For example, if the controller

is configured as 6-phase mode but it is running in

1-phase DCM due to auto phase shedding, a VID

transition command will lead the controller run

into 6-phase CCM immediately.

Over-Clocking

The MP2975 supports 2 types of over-clocking

mode.

1. Tracking Mode

In over-clocking Tracking Mode, the VR

controller adds an offset VID with PMBus

command VOUT_OFFSET (1Eh @ page2).

When the CPU changes VID, the VR

will

provide an output by summing the VID from

CPU SetVID command and VID offset from

VOUT_OFFSET. One exception is when VR

receives SetVID to 0V command from CPU;

the output voltage goes to 0 V and the VID

offset is in-effective.

VOUT_OFFSET (1Eh @ page2) provides -

128 ~ +127 VID steps offset setting. At the

5mV VID table, the max offset is 0.635V and

max Vout is to 2.155V. At the 10mV VID table,

the max offset is 1.27V and max Vout is to 3V.

Tracking mode is effective at SVID, PMBus,

PVID and AVSBus mode all. Write a non-zero

value in VOUT_OFFSET register will enable

over-clocking tracking mode. If VR is on-the-

fly while updating VOUT_OFFSET, the output

voltage will slew to new target immediately.

2. Fix Mode

Fixed voltage margining is used in extreme

over-clocking application where fixed voltage

can provide additional stability. In this mode,

a fixed voltage is commanded with PMBus

command VOUT_COMMAND (21h), and the

VR output voltage will be fixed at this voltage

in regardless of VID changing command from

CPU. When the CPU issues a SetVID

command, the VR will ACK the command,

and assert ALERT# immediately, but keep

the voltage commanded by

VOUT_COMMAND (21h), while the VR

output voltage stays at the fixed VID.

Fix mode is only available at SVID override

mode. To enable over-clocking Fixed Mode,

set MFR_VR_CONFIG1 (68h @ page0), bit

[0] = 1. At the 5mV VID table, the max Vout is

to 2.72V with the VID table extending; at the

10mV VID table, the max Vout is to 3V.

Inductor Current Sensing and Reporting

The MP2975 works with Intelli-Phase to realize

inductor current sensing (see Figure 5). The

cycle by cycle sensed inductor current is used for

multi-phase current balancing, thermal balancing

and per-phase current limitation.

When work with DrMOS which needs external

reference voltage for current sensing, the VDD18

of MP2975 can be used as the reference voltage.

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MP2975：数字多相控制器支持软件动态调压，优化VR13.HC平台供电

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