Cyclone III FPGA开发板详解及参考手册

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本文档是一份关于Cyclone III LSFPGA开发板的详细参考手册，由Altera公司发布，地址位于美国圣何塞市101 Innovation Drive。Cyclone III是 Altera公司的一款FPGA（Field-Programmable Gate Array）系列芯片，适用于各种应用领域，特别是对高性能、低功耗和成本敏感的设计。开发板提供了硬件平台，便于工程师进行Cyclone III芯片的编程和测试。该文档版本为1.0，发布日期为2009年10月，版权全归Altera Corporation所有。文档中包含了Cyclone III FPGA开发板的详细介绍，包括其特性和功能，可能涉及的接口、引脚布局、以及如何通过该板进行硬件设计和编程。此外，还强调了Altera的商标政策，指出除非特别注明，否则所有提及的名称和标志都是Altera的注册商标或服务标记，反映了公司在知识产权保护方面的立场。作为开发工具，Cyclone III LSFPGA开发板可能配备了丰富的特性，如JTAG接口、复用IO引脚、电源管理模块等，以支持用户在硬件设计时实现电路的灵活性和可重构性。开发板可能还提供了用户指南、示例项目、驱动程序和其他必要的软件工具，以便于开发者快速上手和调试设计。值得注意的是，尽管文档提供了标准保修，但Altera保留随时更改产品和服务的权利，并且用户必须在书面协议中明确接受任何改动。同时，Altera对基于文档中的信息、产品或服务的应用或使用不承担任何责任或义务，除非另有明确规定。这份文档是为有经验的FPGA开发人员提供的重要资源，旨在帮助他们充分利用Cyclone III LSFPGA开发板进行高效和精确的设计工作。对于想要在嵌入式系统、通信、信号处理或其他高性能计算应用中使用FPGA的工程师来说，理解和掌握这份文档中的内容至关重要。

2–2 Chapter 2: Board Components

Board Overview

Cyclone III LS FPGA Development Board Reference Manual © October 2009 Altera Corporation

Table 2–1 describes the components and lists their corresponding board references.

Figure 2–1. Overview of the Cyclone III LS FPGA Development Board Features

Clock Input SMAs

Connector (J7, J9)

Max II Reset

Push-Button

Switch (S10)

General User

Push-buttons

Switches

(S3 - S6)

Board Settings

DIP Switch (SW2)

DC Input Jack (J5)

Cyclone III LS FPGA (U15)

Character LCD

(J19)

CPU Reset

Push-button

Switch (S2)

Power Switch (SW1)

General

User DIP

Switch (S7)

General

User LEDs

(D25-D28)

MAX II CPLD

EPM2210 System

Controller (U22)

Clock Output SMA

Connector (J15)

HSMC Port B (J1) HSMC Port A (J2)

Configuration Status

LEDs (D10-D14)

Flash x16 Memory (U9)

DDR2 Memory (U5, U6)

Programmable

Oscillator Output

(J13, J14)

USB Type-B

Connector (J4)

Gigabit Ethernet

Port (J16)

JTAG Connector

(J8)

SSRAM x36

Memory (U14)

Configuration

Select

LEDs

(D29-D31)

Configuration

Program and

Select

Push-buttons

Switches (S8, S9)

Power LED (D3)

JTAG Chain Header

& JTAG Select

Jumpers (J11, J12)

CRC Error (S1)

JTAG Anti-Tamper

Select LEDs (D6-D9)

LCD/HSMC Port B

Data Select (J18)

VCCA Shutdown

Push-Button

Switch (S11)

Table 2–1. Cyclone III LS FPGA Development Board Components (Part 1 of 3)

Board Reference Type Description

Featured Devices

U15 FPGA EP3CLS200F780, 780-pin FBGA.

U22 CPLD EPM2210F256, 256-pin FBGA.

Configuration, Status, and Setup Elements

J4 USB type-B connector Connects to the computer to enable embedded USB-Blaster JTAG.

J11 JTAG chain header Enables and disables devices in the JTAG chain.

J12 Anti-Tamper JTAG select

header

Placing a shunt on this jumper breaks the default JTAG chain, giving

FPGA JTAG signals control to the MAX II EPM2210 System Controller.

D6 Anti-Tamper JTAG select LED Illuminated when the default JTAG chain is broken and the MAX II

EPM2210 System Controller has control of the FPGA JTAG signals.

SW2 Board settings DIP switch Controls the MAX

II CPLD EPM2210 System Controller functions such

as clock enable, SMA clock input control, and which image to load

from flash memory at power-up.

J8 JTAG connector Disables embedded blaster (for use with external USB-Blasters).

D13 Configuration done LED Illuminates when the FPGA is configured.

Chapter 2: Board Components 2–3

Board Overview

D11 Load LED Illuminates when the MAX II CPLD EPM2210 System Controller is

actively configuring the FPGA.

D10 Error LED Illuminates when the FPGA configuration from flash memory fails.

D12 Factory LED Illuminates when the factory image is loaded to the FPGA.

D29, D30, D31 Configuration select LEDs Illuminates to show the LED sequence that determines which flash

memory image loads to the FPGA when PGM SEL is pressed.

D15, D16, D18,

D20, D22

Ethernet LEDs Shows the connection speed as well as transmit or receive activity.

D2 HSMC port A present LED Illuminates when a daughtercard is plugged into the HSMC port A.

D1 HSMC port B present LED Illuminates when a daughtercard is plugged into the HSMC port B.

D3 Power LED Illuminates when 12-V power is present.

J18 LCD/HSMC Port B data select Controls data multiplexing to the FPGA from the LCD or

HSMB_D[65:75]. Placing a shunt on the jumper allows the FPGA to

control the LCD signals.

J6 PS standard/fast select Placing a shunt sets the MSEL pins for passive serial standard

configuration. Otherwise, the MSEL pins is set for passive serial fast

configuration.

S2 CPU reset push-button switch Press to reset the FPGA logic.

S11 VCCA shutdown push-button

switch

Turns VCCA power to the FPGA on and off. This switch initiates a

power-on reset.

S10 MAX II reset push-button

switch

Press to reset the MAX II CPLD EPM2210 System Controller.

S9 PGM select push-button

switch

Toggles the PGM LEDs which selects the program image that loads

from flash memory to the FPGA.

S8 PGM configure push-button

switch

Configure the FGPA from flash memory based on the PGM LEDs

setting.

Clock Circuitry

U17 Programmable oscillator

(125 MHz default)

Programmable oscillator with a default frequency of 125.00 MHz. The

frequency is programmable using the MAX II CPLD EPM2210 System

Controller. For general use such as HSMC logic or gigabit Ethernet

(125 M/156.25 M)

X3 66.6 MHz oscillator 66.6 MHz crystal oscillator for general purpose logic and DDR2

memory.

X5 50 MHz oscillator 50 MHz crystal oscillator for general purpose logic.

Y3 100 MHz oscillator 100 MHz crystal oscillator for configuration purpose.

J7, J9 Clock FPGA input SMAs Drive LVPECL-compatible clock inputs into the clock multiplexer buffer

(U20).

J15 Clock FPGA output SMA Drive out 2.5-V CMOS clock output from the FPGA.

J13, J14 Clock output SMAs LVDS output clock from the clock multiplexer buffer (U20).

General User Input/Output

D25, D26, D27,

D28

User LEDs Four user LEDs. Illuminates when driven low.

S7 User DIP switch Quad user DIP switches. When the switch is ON, a logic 0 is selected.

Table 2–1. Cyclone III LS FPGA Development Board Components (Part 2 of 3)

Board Reference Type Description

2–4 Chapter 2: Board Components

Featured Device: Cyclone III LS Device

The Cyclone III LS FPGA development board features the Cyclone III LS

EP3CLS200F780 device (U15) in a 780-pin FBGA package.

f For more information about Cyclone III device family, refer to the Cyclone III Device

Handbook.

Table 2–2 describes the features of the Cyclone III LS EP3CLS200F780 device.

Table 2–3 lists the Cyclone III LS device component reference and manufacturing

information.

S3, S4, S5, S6 User push-button switches Four user push-button switches. Driven low when pressed.

J19 Character LCD Connector which interfaces to the provided 16 character × 2 line LCD

module.

Memory Devices

U5, U6 DDR2 x16 memory Two independent 16-bit, 64-Mbyte DDR2 devices.

U14 SSRAM x36 memory Standard synchronous RAM which makes a 36-bit 2-Mbyte SSRAM

port.

U9 Flash x16 memory Synchronous burst mode flash device which provides a 16-bit 64-

Mbyte non-volatile memory port.

U21 EEPROM I

C EEPROM

Components and Interfaces

J2 HSMC port A Provides 80 CMOS or 17 LVDS channels per the HSMC specification.

J1 HSMC port B Provides 76 CMOS channels per the HSMC specification.

J16 Gigabit Ethernet RJ-45 connector which provides a 10/100/1000 Ethernet connection

via a Marvell 88E1111 PHY and the FPGA-based Altera Triple Speed

Ethernet MegaCore function in RGMII mode.

Anti-Tamper Interface

J10 JTAG header to MAX II general

I/O

JTAG header connected to general purpose I/O (GPIO) on the MAX II

EPM2210 System Controller.

D8, D9, D10 Anti-Tamper status LEDs Three anti-tamper status indicator LEDs.

S1 CRC error push-button Insert a CRC error when running the anti-tamper example design.

Power Supply

J5 DC input jack Accepts a 14-V – 20-V DC power supply.

SW1 Power switch Switch to power on or off the board when power is supplied from the

DC input jack.

Table 2–1. Cyclone III LS FPGA Development Board Components (Part 3 of 3)

Board Reference Type Description

Table 2–2. Cyclone III LS Device EP3CLS200F780 Features

Equivalent LEs M9K RAM Blocks Total RAM Kbits 18-bit × 18-bit Multipliers PLLs Package Type

198,464 891 8,211 396 4 780-pin FBGA

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