Table of Contents BCM5718 Programmer’s Guide
BROADCOM
June 25, 2012 • 5718-PG106-R Page 20
®
Misc Coalescing Controls ..............................................................................................................259
Broadcom Tagged Status Mode (0x68[9]) ............................................................................260
Clear Interrupt, Mask Interrupt, Mask Mode (0x68[0], 0x68[1], 0x68[8])............................260
Clear Ticks On Rx Bd Events Mode (0x3c00[9]).....................................................................260
No Interrupt On Force Update (0x3c00[11]).........................................................................260
No Interrupt On DMAD Force (0x3c00[12]) ..........................................................................260
Do Not Interrupt On Receives (0x6800[14])..........................................................................260
End of Receive Stream Interrupt ..................................................................................................261
Host Coalescing Mode Register (Offset 0x3c00)...................................................................261
End Stream Debounce Register (Offset 0x3cd4) ...................................................................261
Other Configuration Controls.....................................................................................................................263
Broadcom Mask Mode.........................................................................................................................263
Broadcom Tagged Status Mode...........................................................................................................263
Clear Ticks on BD Events Mode............................................................................................................263
No Interrupt on Force Update .............................................................................................................263
No Interrupt on DMAD Force...............................................................................................................263
Section 12: IO Virtualization (IOV) ................................................................................. 264
Data Structure and Register Changes for IOV............................................................................................265
Mail Box Register Changes...................................................................................................................265
Receive Mail Box Register Changes .....................................................................................................265
Send Mail Box Register Changes..........................................................................................................265
Ring Control Block Changes .................................................................................................................265
VRQ Statistics.......................................................................................................................................265
MSI-X Vectors Changes ........................................................................................................................266
Register Changes..................................................................................................................................266
IOV - Receive Side.......................................................................................................................................267
IOV - Transmit Side.....................................................................................................................................268
Section 13: Ethernet Controller Register Definitions...................................................... 270
BCM5718 Family Register MAP..................................................................................................................270
PCI Configuration Registers........................................................................................................................272
Device ID and Vendor ID Register (offset: 0x00)..................................................................................272
Status and Command Register (offset: 0x04) ......................................................................................272
PCI Classcode and Revision ID Register (offset: 0x08) .........................................................................274
BIST, Header Type, Latency Timer, Cache Line Size Register (offset: 0x0C) ........................................274
Base Address Register 1 (offset: 0x10) ................................................................................................275
Base Address Register 2 (offset: 0x14) ................................................................................................275