2019年IEEE固态电路期刊特刊精华：微电子器件与设计突破

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《JSSC-2019-4》是一期IEEE Journal of Solid-State Circuits的特刊，专注于固体状态电路的设计，特别是集成电路的晶体管级设计。该期刊每月发表论文，遵循严格的同行评审过程，确保学术质量。文章在被接受之前会经过抄袭检测。本期特刊包含了多篇前沿研究论文，涵盖了各种关键领域： 1. **标题**："Introduction to the Special Issue on the 2018 Symposium on VLSI Circuits" - K. Chang and K. Takeuchi的文章开启了特刊，可能介绍了2018年大规模集成电路（VLSI）研讨会的重要成果和技术趋势。 2. **论文**： - **Chip-Scale Molecular Clock** - C.Wang等人提出了一种芯片尺度分子钟技术，展示了微小化和高性能的时间基准解决方案。 - **Ultra-Low-Jitter 22.8-GHz Ring-LC-Hybrid Injection-Locked Clock Multiplier** - S.Choi等人的工作关注于高精度的时钟乘法器设计，其具有极低的抖动和114倍的乘法因子。 - **12-Bit 1-MS/s SAR ADC with On-Chip Input-Signal-Independent Calibration** - J.Shen等人介绍了一款功耗极低、线性度高的12位模数转换器，利用内置校准技术实现出色的信噪比。 3. **放大器设计**： - **1-mW Class-AB Amplifier** - N.Mehta等人设计了一款适用于高质量16路耳机的低功耗、高保真类-AB放大器，采用65纳米CMOS工艺。 4. **能量效率优化**： - **Hybrid Structure Dual-Path Step-Down Converter** - Y.Huh等人提出了一种能效高达96.2%的双路径降压转换器，利用大电感器以提升系统性能。 5. **创新ADC设计**： - **0.5-1.1-V Adaptive Bypassing SAR ADC** - Z.Ding和X.Zhou的贡献在于设计了一种利用电压控制振荡器（VCO）比较器周期信息的自适应旁路型SAR ADC，旨在提高能效和性能。这些论文代表了当前集成电路设计的最新进展，涉及高频时钟设计、高性能数据转换、低功耗放大器以及电源管理等领域，反映出VLSI技术在满足不断增长的电子设备性能需求方面的创新与突破。

1188 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 54, NO. 4, APRIL 2019

Fig. 4. Overall block diagram of the proposed IC.

Fig. 5. Proposed CRLNA circuit.

noise of integrator cannot be avoided. This can be explained

by the following equations:

EDO,max



DSL1



(2)

ni,DSL



DSL1





n,INT.



DSL1





(3)

where V

EDO,max

is the maximum EDO rejection range,

n,INT.

is the output noise of the integrator, and V

ni,DSL

the noise contribution of DSL at the LNA input. Because

EDO,max

and V

ni,DSL

are both proportional to the capac-

itance ratio (C

DSL1

), it is hard to achieve high

EDO rejection range and low input-referred noise at the same

time.

To solve this problem, previous mixed-mode DSL imple-

mentation [14] is presented in Fig. 7(b). It uses a coarse digital

DSL and a ﬁne analog DSL to decrease overall LNA noise

while maintaining the cancellation range. The EDO rejection

range and noise contribution are

EDO,max



DSL1

+ C

DSL2



(4)

Fig. 6. Proposed current reusing OTA. (a) Schematic of OTAs. (b) Equivalent

block diagram for CM signal analysis.

ni,DSL



+ C

DSL1

+ C

DSL2





n,INT



DSL1





(5)

where C

DSL1

is the capacitor for the integrator, and C

DSL2

the capacitor for the clock generator. For the same EDO

rejection range, C

DSL1

can be smaller than [13], and results in

decreased noise contribution of analog integrator. However,

DSL1

+ C

DSL2

is constant in this implementation, it still

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Fig. 7. Voltage mode DSL architectures. (a) Conventional analog implementation [13]. (b) Mixed-mode implementation [14]. (c) Proposed BDSL.

Fig. 8. Schematic of BDSL.

suffers from the noise ampliﬁcation factor (NAF)

NAF =

+ C

DSL1

+ C

DSL2

. (6)

Therefore, in this paper, we proposed BDSL using the boot-

strapping clock generator. BDSL reduces the LNA noise

further by cutting C

DSL2

by half. Fig. 8 shows the schematic

of BDSL. Bootstrapping capacitor is included to boost up

to 2V

clock to reduce the size of C

DSL2

by half for

the same EDO rejection. As shown in Fig. 9, at 350-mV

EDO condition, NAF is 14.2% lower than that of [14]. Since

BDSL requires a large on-chip capacitor of 50 pF, the chip

area of IA should be sacriﬁced. In this paper, the proposed

EEG IA is implemented with the chip area of 0.105 mm

per channel which is ﬁve times larger than [13]. However,

the chip area of IA is less important in ear-EEG applications

because the required number of channels is smaller than that in

on-scalp EEG applications.

Fig. 10 shows the measurement results of EEG LNA includ-

ing two key features, CRLNA and BDSL. The CM and differ-

ential mode gain is represented in Fig. 10(a). The linear gain

of 40 dB is achieved by the high open-loop gain of CRLNA.

The measured CMRR is 95 dB over the ampliﬁer bandwidth

which is 25 dB larger than [15] because of added current

source in CRLNA. The ripple reduction loop rejects the ripple

component at the chopping frequency. The BDSL generates

the 0.5-Hz high-pass ﬁlter (HPF) corner for the EDO rejection.

Fig. 10(b) shows the output noise spectrum of different

Fig. 9. Relationship between bootstrapping voltage and NAF.

EDO conditions. CRLNA achieves the 0.32 μV

rms

input-

referred noise over 0.5–100 Hz in the presence of

20-mV EDO. When the EDO is increased to 350 mV, the noise

level is increased due to the required DSL capacitance (C

DSL2

)

size became larger. However, BDSL can reduce the required

DSL2

by half of [14]; the input-referred noise is measured

as 0.38 μV

rms

Table II shows the performance comparison of EEG readout.

EEG LNAs are represented which can cover the large EDO

to sense the signal non-invasively. Among them, the proposed

LNA shows the state-of-the-art power efﬁciency factor (PEF)

[15] of 8.8 with the large EDO rejection range up to 350 mV.

Moreover, the proposed LNA shows low input-referred noise

of 0.38 μV

rms

and noise efﬁciency factor (NEF) of 3.32 [17].

Considering the power consumption of entire AFE

(1-Ch EEG LNA, PGA, and ADC), the proposed IC consumes

5 μW, and the 11.8 PEF is measured. The PEF performance

is slightly worse than [20]; however, the EDO rejection range

is seven times larger. The proposed EEG LNA has the small

differential input range rather than the latest neural recording

readout [21]. However, ±0.4-mV differential input is large

enough to measure the ear-EEG signal because its amplitude

is 10–15 dB smaller than the maximum amplitude of on-scalp

EEG, 0.3 mV.

C. DMPGA

The intentional blink is responsible for BCI activation in

sleep mode; the accurate and power-efﬁcient blink detection

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Fig. 12. Gain transfer curve of DMPGA.

and 100 V/V. However, in the sleep mode, C

is driven to

the output CM voltage of the PGA by periodic pulse signal

CLK

RESET

,andC

acts as a sampling capacitor. When the

switches are opened, only the voltage differences ampliﬁed by

the PGA, resulting in a differentiator to detect the transition

edges without ECG artifacts. EMG and power line artifact are

rejected by the switched capacitor low-pass ﬁlter. As a result,

in the sleep mode, the bandwidth of DMPGA is narrowed

to 10–20 Hz for artifact rejection. After the ﬁltering process,

the intentional blink is identiﬁed by the comparator with

a threshold. By setting a threshold (V

= 200 mV and

PGA

= 10 V/V), the spontaneous blink can be successfully

ignored among nine subjects.

Fig. 12 shows the measured transfer curve of the DMPGA.

The bandwidth can be controlled depending on the operation

mode, 0.5–100 Hz for the active mode and 10–20 Hz for the

sleep mode. In the sleep mode, CRLNA, DMPGA, and min-

imal digital blocks are activated and consuming a low power

of 5.7 μW, and in the active mode, the proposed IC consumes

82.9 μW for the ear-EEG sensing and transmission.

IV. M

EASUREMENT AND IMPLEMENTATION RESULTS

A. Chip Implementation Results

Fig. 13 and Table III show the chip micrograph and a

performance summary. The chip is fabricated in 65-nm CMOS

process with 8 mm

. The IC consumes 82.9 μW in the active

mode and 5.7 μW in the sleep mode. Thanks to the CRLNA

and BDSL, the proposed IC can measure ear-EEG with the

state-of-the-art 8.8 PEF even on 350-mV EDO condition of

dry electrodes. DMPGA allows accurate mode switching to

reduce system power consumption.

B. System Implementation Results

Fig. 14 shows the measured ASSR response using the

proposed system. Using a pair of in-ear module, the 37 (with

1-kHz carrier frequency) and 43 Hz (with 2.5-kHz carrier

frequency) modulated sound stimuli are applied to the left

and right ear simultaneously. Since the carrier frequency is

different, user can distinguish two sound stimuli through the

pitch of the sound. The output spectrum response shows

that corresponding frequency tone can be discriminated with

respect to user’s attention.

Fig. 13. Chip micrograph.

Fig. 14. Measurement results of ASSR response. The 37- and 43-Hz sound

stimuli are applied to the left and right ear simultaneously. (a) EEG spectrum

with user’s left attention. (b) EEG spectrum with user’s right attention.

Fig. 15. ASSR amplitude comparison results during repetitive measurements.

(a) EEG power at 37 Hz with left and right attentions. (b) EEG power at 43 Hz

with left and right attentions.

Fig. 15 shows the results of the measurement how

much ASSR increases according to the concentration at

each stimulation frequency. The averaged ASSR amplitude

increased 2.92× for the 37-Hz stimulus, and 1.92× for the

43-Hz stimulus. The difference of amplitude increase is due

to the hearing ability of the subject [3]. In this case, the exper-

iment indicates that the subject can hear the low pitch sound

better than the high pitch sound.

1192 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 54, NO. 4, APRIL 2019

Fig. 16. Measured spectrogram of ear-EEG signal with consecutive attention patterns.

TABLE III

HIP PERFORMANCE SUMMARY

Fig. 16 shows the measured spectrogram. Spectrogram is

the representation of the frequency spectrum that varies over

time. In this measurement, the subject tends to focus on

the multiple directions. Each attention lasts for 15 s. The

spectrogram results are in good accordance with the four

classes of attentions, right-right (RR) attention, right-left (RL)

attention, left-right-right (LRR) attention, and left-left-right

(LLR) attention. The combination of consecutive selections

is clearly distinguished on the spectrogram so that the combi-

nation of attention directions can be the command signals to

control the device.

Fig. 17 shows the classiﬁcation accuracy results of binary

selection task. The nine subjects participated in the exper-

iment. Each subject performed L or R attentions of the

speciﬁed pattern during 100 trials. The measured 4-Ch ear-

EEG signal was transmitted to an external device and used as

the training data for linear SVM classiﬁer. The classiﬁcation

accuracy was evaluated with an additional 100 trials. The

attention time for each trial was the independent variables for

the experiment. As the concentration time increased, the accu-

racy tended to increase and an average of 84% accuracy was

Fig. 17. Classiﬁcation accuracy results of linear SVM in the external device.

Fig. 18. System power breakdown.

obtained at 15 s. An accuracy of 84% and an attention time

of 15 s are not yet available as a UI for the general public, but it

can be used as a convenient and non-substitutable input device

for patients with poor athletic ability. Also, combining with

additional domains such as accelerometer and gyro sensors can

effectively improve the accuracy and decision-making time.

Fig. 18 shows the system power breakdown. Since the

average system power consumption is determined by the busy

rate of the active mode, we measured the power consumption

of each mode separately. In the active mode, all system

building blocks are activated to generate the sound stimuli

and measure the ASSR. Also, the BCC TRX in BCI IC trans-

mits the recorded signals. BCC TRX consumes 0.4-mA peak

current consumption, while the commercial Bluetooth low-

energy transceiver consumes 8 mA [23]. The entire peak power

consumption of active mode is 12.3 mW which is available

to continuously operate more than 10 h with the small Li-ion

battery (3.7 V and 40 mAh) of 0.324 cm

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2019年IEEE固态电路期刊特刊精华：微电子器件与设计突破

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