PSD4235G2：5V供电的16位MCU Flash ISP技术详解

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PSD4235G2是一款专为16位微控制器设计的Flash In-System Programmable (ISP) 芯片，它在5V供电环境下提供高级功能和灵活性。该芯片的核心特性包括： 1. 双银行闪存存储器： - 主闪存有4Mbit的容量（共8个均匀分段的32Kx16字节区块），提供了大容量的数据存储空间。 - 次级闪存有256Kbit，分为4个独立的区块，支持并发操作，可以在读取一个闪存的同时进行其他闪存的擦除和写入。 2. 电池备份的64Kbit SRAM： - 提供了非易失性数据存储，即使在无电源的情况下也能保持数据。 3. 高性能可编程逻辑器件（PLD）： - 包含超过3000个门的PLD，包括CPLD和DPLD，具备强大的逻辑处理能力。 - CPLD具有16个输出宏细胞（OMCs）和24个输入宏细胞（IMCs），用户可以根据需求自定义内部芯片选择解码。 4. 多功能I/O端口： - 共有7个独立的L/O端口，每个包含52个可配置的I/O引脚，可以用于MCU I/O、PLD I/O、捕获或锁存的地址输出、特殊功能I/O以及开放漏极输出模式，为外部连接提供了多种可能性。 5. In-System Programming (ISP) 与JTAG支持： - 内置JTAG兼容的串行接口，实现全芯片级别的在线编程，简化了生产和测试流程。 - 通过低成本的FlashLINK电缆，用户可以直接从个人电脑进行编程操作，提高了开发效率。 6. 页面寄存器： - 芯片内建的页面寄存器有助于扩展微控制器的地址空间，增加了系统灵活性和可扩展性。 PSD4235G2是一款高性能且灵活的嵌入式控制芯片，集成了大容量闪存、电池备份内存、PLD功能、多用途I/O端口和JTAG ISP技术，适用于对程序升级、数据存储和I/O灵活性有高要求的应用场景，如工业控制、物联网设备、消费电子等领域。

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PSD ARCHITECTURAL OVERVIEW

PSD devices contain several major functional

blocks. Figure 4 shows the architecture of the PSD

device family. The functions of each block are de-

scribed briefly in the following sections. Many of

the blocks perform multiple functions and are user

configurable.

Memory

Each of the memory blocks is briefly discussed in

the following paragraphs. A more detailed discus-

sion can be found in the section entitled “Memory

Blocks“ on page 25.

The 4 Mbit primary Flash memory is the main

memory of the PSD. It is divided into 8 equally-

sized sectors that are individually selectable.

The 256 Kbit secondary Flash memory is divided

into 4 equally-sized sectors. Each sector is individ-

ually selectable.

The 64 Kbit SRAM is intended for use as a

scratch-pad memory or as an extension to the

MCU SRAM. If an external battery is connected to

the PSD’s Voltage Stand-by (V

STBY

, PE6) signal,

data is retained in the event of power failure.

Each memory block can be located in a different

address space as defined by the user. The access

times for all memory types includes the address

latching and DPLD decoding time.

PLDs

The device contains two PLD blocks, the Decode

PLD (DPLD) and the Complex PLD (CPLD), as

shown in Table 3, each optimized for a different

function. The functional partitioning of the PLDs

reduces power consumption, optimizes cost/per-

formance, and eases design entry.

The DPLD is used to decode addresses and to

generate Sector Select signals for the PSD inter-

nal memory and registers. The DPLD has combi-

natorial outputs, while the CPLD can implement

more general user-defined logic functions. The

CPLD has 16 Output Macrocells (OMC) and 8

combinatorial outputs. The PSD also has 24 Input

Macrocells (IMC) that can be configured as inputs

to the PLDs. The PLDs receive their inputs from

the PLD Input Bus and are differentiated by their

output destinations, number of product terms, and

Macrocells.

The PLDs consume minimal power. The speed

and power consumption of the PLD is controlled

by the Turbo Bit in PMMR0 and other bits in

PMMR2. These registers are set by the MCU at

run-time. There is a slight penalty to PLD propaga-

tion time when not in the Turbo mode.

I/O Ports

The PSD has 52 I/O pins divided among seven

ports (Port A, B, C, D, E, F and G). Each I/O pin

can be individually configured for different func-

tions. Ports can be configured as standard MCU I/

O ports, PLD I/O, or latched address outputs for

MCUs using multiplexed address/data buses

The JTAG pins can be enabled on Port E for In-

System Programming (ISP).

MCU Bus Interface

The PSD easily interfaces easily with most 16-bit

MCUs, either with multiplexed or non-multiplexed

address/data buses. The device is configured to

respond to the MCU’s control pins, which are also

used as inputs to the PLDs.

ISP via JTAG Port

In-System Programming (ISP) can be performed

through the JTAG signals on Port E. This serial in-

terface allows complete programming of the entire

PSD device. A blank device can be completely

programmed. The JTAG signals (TMS, TCK,

TSTAT, TERR

, TDI, TDO) can be multiplexed with

other functions on Port E. Table 4 indicates the

JTAG pin assignments.

Table 3. PLD I/O

Table 4. JTAG SIgnals on Port E

Name Inputs Outputs

Product

Terms

Decode PLD (DPLD) 82 17 43

Complex PLD (CPLD) 82 24 150

Port E Pins JTAG Signal

PE0 TMS

PE1 TCK

PE2 TDI

PE3 TDO

PE4 TSTAT

PE5 TERR

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All the registers of the PSD are included here, for

reference. Detailed descriptions of these registers

can be found in the following sections.

Table 7. Data-In Registers - Ports A, B, C, D, E, F, G

Note: Bit Definitions (Read-only registers):

Read Port pin status when Port is in MCU I/O input mode.

Table 8. Data-Out Registers - Ports A, B, C, D, E, F, G

Note: Bit Definitions:

Latched data for output to Port pin when pin is configured in MCU I/O output mode.

Table 9. Direction Registers - Ports A, B, C, D, E, F, G

Note: Bit Definitions:

Port pin 0 = Port pin is configured in Input mode (default).

Port pin 1 = Port pin is configured in Output mode.

Table 10. Control Registers - Ports E, F, G

Note: Bit Definitions:

Port pin 0 = Port pin is configured in MCU I/O mode (default).

Port pin 1 = Port pin is configured in Latched Address Out mode.

Table 11. Drive Registers - Ports A, B, D, E, G

Note: Bit Definitions:

Port pin 0 = Port pin is configured for CMOS Output driver (default).

Port pin 1 = Port pin is configured for Open Drain output driver.

Table 12. Drive Registers - Ports C, F

Note: Bit Definitions:

Port pin 0 = Port pin is configured for CMOS Output driver (default).

Port pin 1 = Port pin is configured in Slew Rate mode.