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FPGA

XQV100

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DS002 (v1.2) February 13, 2001 www.xilinx.com 1

Preliminary Product Specification 1-800-255-7778

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

Features

• Certified to MIL-PRF-38535 (Qualified Manufacturer

Listing)

• Guaranteed over the full military temperature range

(–55°C to +125°C)

• Ceramic and Plastic Packages

• Fast, high-density Field-Programmable Gate Arrays

- Densities from 100K to 1M system gates

- System performance up to 200 MHz

- Hot-swappable for Compact PCI

• Multi-standard SelectI/O™ interfaces

- 16 high-performance interface standards

- Connects directly to ZBTRAM devices

• Built-in clock-management circuitry

- Four dedicated delay-locked loops (DLLs) for

advanced clock control

- Four primary low-skew global clock distribution

nets, plus 24 secondary global nets

• Hierarchical memory system

- LUTs configurable as 16-bit RAM, 32-bit RAM,

16-bit dual-ported RAM, or 16-bit Shift Register

- Configurable synchronous dual-ported 4K-bit

RAMs

- Fast interfaces to external high-performance RAMs

• Flexible architecture that balances speed and density

- Dedicated carry logic for high-speed arithmetic

- Dedicated multiplier support

- Cascade chain for wide-input functions

- Abundant registers/latches with clock enable, and

dual synchronous/asynchronous set and reset

- Internal 3-state bussing

- IEEE 1149.1 boundary-scan logic

- Die-temperature sensing device

• Supported by FPGA Foundation™ and Alliance

Development Systems

- Complete support for Unified Libraries, Relationally

Placed Macros, and Design Manager

- Wide selection of PC and workstation platforms

• SRAM-based in-system configuration

- Unlimited reprogrammability

- Four programming modes

• 0.22 µm 5-layer metal process

• 100% factory tested

Description

The QPRO™ Virtex™ FPGA family delivers high-perfor-

mance, high-capacity programmable logic solutions. Dra-

matic increases in silicon efficiency result from optimizing

the new architecture for place-and-route efficiency and

exploiting an aggressive 5-layer-metal 0.22 µm CMOS pro-

cess. These advances make QPRO Virtex FPGAs powerful

and flexible alternatives to mask-programmed gate arrays.

The Virtex family comprises the four members shown in

Table 1.

Building on experience gained from previous generations of

FPGAs, the Virtex family represents a revolutionary step

forward in programmable logic design. Combining a wide

variety of programmable system features, a rich hierarchy of

fast, flexible interconnect resources, and advanced process

technology, the QPRO Virtex family delivers a high-speed

and high-capacity programmable logic solution that

enhances design flexibility while reducing time-to-market.

Refer to the “Virtex™ 2.5V Field Programmable Gate

Arrays” commercial data sheet for more information on

device architecture and timing specifications.

QPRO Virtex 2.5V QML

High-Reliability FPGAs

DS002 (v1.2) February 13, 2001

Preliminary Product Specification

Table 1: QPRO Virtex Field-Programmable Gate Array Family Members

Device System Gates CLB Array Logic Cells

Maximum

Available I/O Block RAM Bits

Max Select

RAM Bits

XQV100 108,904 20 x 30 2,700 180 40,960 38,400

XQV300 322,970 32 x 48 6,912 316 65,536 98,304

XQV600 661,111 48 x 72 15,552 316 98,304 221,184

XQV1000 1,124,022 64 x 96 27,648 404 131,072 393,216

QPRO Virtex 2.5V QML High-Reliability FPGAs

DS002 (v1.2) February 13, 2001 www.xilinx.com 3

Preliminary Product Specification 1-800-255-7778

Recommended Operating Conditions

DC Characteristics Over Recommended Operating Conditions

Symbol Description Min Max Units

CCINT

Supply voltage relative to GND, T

= –55°C to +125°C Ceramic packages 2.5 – 5% 2.5 + 5% V

Supply voltage relative to GND, T

= –55°C to +125°C Plastic packages 2.5 – 5% 2.5 + 5% V

CCO

Supply voltage relative to GND, T

= –55°C to +125°C Ceramic packages 1.2 3.6 V

Supply voltage relative to GND, T

= –55°C to +125°C Plastic packages 1.2 3.6 V

Input signal transition time - 250 ns

Initialization Temperature Range

XQVR300 - 55 +125 °C

XQVR600 - 40 +125 °C

XQVR1000 - 40 +125 °C

Operational Temperature Range

XQVR300 - 55 +125 °C

XQVR600 - 55 +125 °C

XQVR1000 - 55 +125 °C

Notes:

1. Correct operation is guaranteed with a minimum V

CCINT

of 2.25V (Nominal V

CCINT

– 10%). Below the minimum value stated above,

all delay parameters increase by 3% for each 50 mV reduction in V

CCINT

below the specified range.

2. At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per

°C.

3. Input and output measurement threshold is ~50% of V

4. Initialization occurs from the moment of VCC ramp-up to the rising transition of the INIT pin.

5. The device is operational after the INIT pin has transitioned high.

Symbol Description Device Min Max Units

DRINT

Data retention V

CCINT

voltage

(below which configuration data may be lost)

All 2.0 - V

DRIO

Data retention V

CCO

voltage

(below which configuration data may be lost)

All 1.2 - V

CCINTQ

Quiescent V

CCINT

supply current

(1)

XQV100 - 50 mA

XQV300 - 75 mA

XQV600 - 100 mA

XQV1000 - 100 mA

CCOQ

Quiescent V

CCINT

supply current

(1)

XQV100 - 2 mA

XQV300 - 2 mA

XQV600 - 2 mA

XQV1000 - 2 mA

REF

current per V

REF

pin - - 20 µA

Input or output leakage current - –10 +10 µA

Input capacitance (sample tested) - - 8 pF

RPU

Pad pull-up (when selected) at V

= 0V, V

CCO

= 3.3V (sample tested) -

(2)

0.25 mA

RPD

Pad pull-down (when selected) at V

= 3.6V (sample tested) -

(2)

0.15 mA

Notes:

1. With no output current loads, no active input pull-up resistors, all I/O pins in a High-Z state and floating.

2. Internal pull-up and pull-down resistors guarantee valid logic levels at unconnected input pins. These pull-up and pull-down resistors

do not guarantee valid logic levels when input pins are connected to other circuits.

QPRO Virtex 2.5V QML High-Reliability FPGAs

DS002 (v1.2) February 13, 2001 www.xilinx.com 5

Preliminary Product Specification 1-800-255-7778

Virtex Switching Characteristics

Testing of switching parameters is modeled after testing

methods specified by MIL-M-38510/605. All devices are

100% functionally tested. Internal timing parameters are

derived from measuring internal test patterns. Listed below

are representative values. For more specific, more precise,

and worst-case guaranteed data, use the values reported

by the static timing analyzer (TRCE in the Xilinx Develop-

ment System) and back-annotated to the simulation netlist.

All timing parameters assume worst-case operating condi-

tions (supply voltage and junction temperature). Values

apply to all Virtex devices unless otherwise noted.

IOB Input Switching Characteristics

Input delays associated with the pad are specified for

LVTTL levels. For other standards, adjust the delays with

the values shown in "IOB Input Switching Characteristics

Standard Adjustments" on page 6.

Symbol Description Device

Speed

Grade

Units-4

Propagation Delays

IOPI

Pad to I output, no delay All 1.0 ns, max

IOPID

Pad to I output, with delay XQV100 1.9 ns, max

XQV300 1.9 ns, max

XQV600 2.3 ns, max

XQV1000 2.7 ns, max

IOPLI

Pad to output IQ via transparent latch, no delay All 2.0 ns, max

IOPLID

Pad to output IQ via transparent latch, with delay XQV100 4.8 ns, max

XQV300 5.1 ns, max

XQV600 5.5 ns, max

XQV1000 5.9 ns, max

Sequential Delays

IOCKIQ

Clock CLK to output IQ All 0.8 ns, max

Setup and Hold Times with Respect to Clock CLK Setup Time / Hold Time

IOPICK

/ T

IOICKP

Pad, no delay All 2.0 / 0 ns, min

IOPICKD

/ T

IOICKPD

Pad, with delay All 5.0 / 0 ns, min

IOICECK

/ T

IOCKICE

ICE input All 1.0 / 0 ns, min

IOSRCKI

/ T

IOCKISR

SR input (IFF, synchronous) All 1.3 / 0 ns, min

Set/Reset Delays

IOSRIQ

SR input to IQ (asynchronous) All 1.8 ns, max

GSRQ

GSR to output IQ All 12.5 ns, max

Notes:

1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but

if a “0” is listed, there is no positive hold time.

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