AMD Family 17h Model 31h处理器编程参考指南

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"AMD Family 17h Model 31h, Revision B0处理器的初步编程参考手册(Preliminary Processor Programming Reference, PPR)是由AMD公司发布的一份开放文档，旨在为开发者提供该处理器系列的详细编程指南。这份文档的最新版本是55803 Rev 0.91，发布日期为2020年9月1日。手册涵盖了重要的技术细节，包括但不限于处理器架构、指令集、接口规范、性能优化技巧以及安全注意事项。在使用过程中，读者需要注意，AMD明确保留所有权利，此文档提供的信息仅为信息性用途，可能会有技术上的不准确、遗漏或排版错误。AMD并不保证文档内容的完全准确性和完整性，也不对因使用AMD硬件、软件或相关产品产生的问题承担任何法律责任。此外，文档并未授予用户任何知识产权许可，使用这些信息时应遵循AMD的许可条款。 PPR手册特别强调，由于技术进步和不断更新，信息可能会随时发生变化，因此开发者在编程时需保持与AMD官方的最新沟通，以确保代码的兼容性和最佳性能。它适合于需要深入了解AMD处理器内部工作原理、编写高效能驱动程序或应用开发人员使用。对于深入研究、调试或优化AMD Family 17h Model 31h处理器的工程师来说，这是一份不可或缺的参考资料。"

55803 Rev 0.91 - Sep 1, 2020 PPR for AMD Family 17h Model 31h B0

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1.4 Conventions

1.4.1 Numbering

• Binary numbers: Binary numbers are indicated either by appending a "b" at the end (e.g., 0110b) or by verilog

syntax (e.g., 4'b0110).

• Hexadecimal numbers: Hexadecimal numbers are indicated by appending an "h" to the end (e.g., 45F8h) or by

verilog syntax (e.g., 16'h45F8).

• Decimal numbers: A number is decimal if not specified to be binary or hex.

• Exception: Physical register mnemonics are implied to be hex without the h suffix.

• Underscores in numbers: Underscores are used to break up numbers to make them more readable. They do not

imply any operation (e.g., 0110_1100).

1.4.2 Arithmetic And Logical Operators

In this document, formulas generally follow Verilog conventions for logic equations.

Table 2: Arithmetic and Logical Operator Definitions

Operator Definition

{} Concatenation. Curly brackets are used to indicate a group of bits that are concatenated together.

Each set of bits is separated by a comma (e.g., {Addr[3:2], Xlate[3:0]} represents a 6-bit values;

the two MSBs are Addr[3:2] and the four LSBs are Xlate[3:0]).

| Bitwise OR (e.g., 01b | 10b == 11b).

|| Logical OR (e.g., 01b || 10b == 1b). It treats a multi-bit operand as 1 if >= 1 and produces a 1-bit

result.

& Bitwise AND (e.g., 01b & 10b == 00b).

&& Logical AND (e.g., 01b && 10b == 1b). It treats a multi-bit operand as 1 if >= 1 and produces a 1-

bit result.

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^ Bitwise exclusive-OR (e.g., 01b ^ 10b == 11b). Sometimes used as "raised to the power of" as

well, as indicated by the context in which it is used (e.g., 2^2 == 4).

~ Bitwise NOT (also known as one's complement). (e.g., ~10b == 01b).

! Logical NOT (e.g., !10b == 0b). It treats a multi-bit operand as 1 if >= 1 and produces a 1-bit

result.

<, <=, >,

>=, ==, !=

Relational. Less than, Less than or equal, greater, greater than or equal, equal, and not

equal.

+, -, *, /,

Arithmetic. Addition, subtraction, multiplication, division, and modulus.

<< Bitwise left shift. Shift left first operand by the number of bits specified by the 2nd

operand (e.g., 01b << 01b == 10b).

>> Bitwise right shift. Shift right first operand by the number of bits specified by the 2nd

operand (e.g., 10b >> 01b == 01b).

?: Ternary conditional (e.g., condition ? value if true : value if false).

Table 3: Function Definitions

Term Description

ABS ABS(integer expression): Remove sign from signed value.

FLOOR FLOOR(integer expression): Rounds real number down to nearest integer.

CEIL CEIL(real expression): Rounds real number up to nearest integer.

MIN MIN(integer expression list): Picks minimum integer or real value of comma separated list.

MAX MAX(integer expression list): Picks maximum integer or real value of comma separated list.

COUNT COUNT(integer expression): Returns the number of binary 1's in the integer.

ROUND ROUND(real expression): Rounds to the nearest integer; halfway rounds away from zero.

UNIT UNIT(register field reference): Input operand is a register field reference that contains a valid values table

that defines a value with a unit (e.g., clocks, ns, ms, etc). This function takes the value in the register field

and returns the value associated with the unit (e.g., If the field had a valid value definition where 1010b was

defined as 5 ns). Then if the field had the value of 1010b, then UNIT() would return the value 5.

POW POW(base, exponent): POW(x,y) returns the value x to the power of y.

1.4.2.1 Operator Precedence and Associativity

This document follows C operator precedence and associativity. The following table lists operator precedence (highest to

lowest). Their associativity indicates in what order operators of equal precedence in an expression are applied. Parentheses

are also used to group subexpressions to force a different precedence; such parenthetical expressions can be nested and are

evaluated from inner to outer (e.g., "X = A || !B && C" is the same as "X = A || ((!B) && C)").

Table 4: Operator Precedence and Associativity

Operator Description Associativity

!, ~ Logical negation/bitwise complement right to left

*, /, % Multiplication/division/modulus left to right

+, - Addition/subtraction left to right

<<, >> Bitwise shift left, Bitwise shift right left to right

< , <=, >,

>=, ==, !=

Relational operators left to right

& Bitwise AND left to right

^ Bitwise exclusive OR left to right

| Bitwise inclusive OR left to right

&& Logical AND left to right

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|| Logical OR left to right

?: Ternary conditional right to left

1.4.3 Register Mnemonics

A register mnemonic is a short name that uniquely refers to a register, either all instances of that register, some instances,

or a single instance.

Every register instance can be expressed in 2 forms, logical and physical, as defined below.

Table 5: Register Mnemonic Definitions

Term Description

logical mnemonic The register mnemonic format that describes the register functionally, what namespace to

which the register belongs, a name for the register that connotes its function, and optionally,

named parameters that indicate the different function of each instance (e.g.,

Link::Phy::PciDevVendIDF3). See 1.4.3.1 [Logical Mnemonic].

physical mnemonic The register mnemonic that is formed based on the physical address used to access the

1.4.3.1 Logical Mnemonic

The logical mnemonic format consists of a register namespace, a register name, and optionally a register instance specifier

(e.g., register namespace::register name register instance specifier).

For Unb::PciDevVendIDF3:

• The register namespace is Unb, which is the UNB IP register namespace.

• The register name is PciDevVendIDF3, which reads as PCICFG device and vendor ID in Function 3.

• There is no register instance specifier because there is just a single instance of this register.

For Dct::Phy::CalMisc2_dct[1:0]_chiplet[BCST,3:0]_pad[BCST,11:0]:

• The register namespace is Dct::Phy, which is the DCT PHY register namespace.

• The register name is CalMisc2, which reads as miscellaneous calibration register 2.

• The register instance specifier is _dct[1:0]_chiplet[BCST,3:0]_pad[BCST,11:0], which indicates that there are 2

DCTPHY instances, each IP for this register has 5 chiplets (0-3 and BCST), and for each chiplet 13 pads (0-11 and

BCST). This register has 130 instances. (2*5*13)

Table 6: Logical Mnemonic Definitions

Term Description

indicates to which IP it belongs and an IP may have multiple namespaces. A

namespace is a string that supports a list of "::" separated names. The convention is

for the list of names to be hierarchical, with the most significant name first and the

least significant name last (e.g., Link::Phy::Rx is the RX component in the Link

PHY).

parameter specifier (e.g., The register instance specifier

_dct[1:0]_chiplet[BCST,3:0]_pad[BCST,11:0] consists of 3 register instance

parameter specifiers, _dct[1:0], _chiplet[BCST,3:0], and _pad[BCST,11:0]).

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specifier

A register instance parameter specifier is of the form _register parameter

name[register parameter value list] (e.g., The register instance parameter specifier

_dct[1:0] has a register parameter name of dct (The DCT PHY instance name) and

a register parameter value list of "1:0" or 2 instances of DCT PHY).

the logical hierarchy (e.g., The register parameter name dct specifies how many

instances of the DCT PHY exist).

the logical names 0 and 1, but it should be noted that the logical names 0 and 1 can

correspond to physical values other than 0 and 1). It is the purpose of the

AddressMappingTable to map these register parameter values to physical address

values for the register.

1.4.3.2 Physical Mnemonic

The physical register mnemonic format varies by the access method. The following table describes the supported physical

Table 7: Physical Mnemonic Definitions

Term Description

PCICFG The PCICFG, or PCI defined configuration space, physical register mnemonic format

is of the form DXFYxZZZ.

BAR The BAR, or base address register, physical register mnemonic format is of the form

PREFIXxZZZ.

MSR The MSR, or x86 model specific register, physical register mnemonic format is of the

form MSRXXXX_XXXX, where XXXX_XXXX is the hexadecimal MSR number.

This space is accessed through x86 defined RDMSR and WRMSR instructions.

PMC The PMC, or x86 performance monitor counter, physical register mnemonic format is

any of the forms {PMCxXXX, L2IPMCxXXX, NBPMCxXXX}, where XXX is the

performance monitor select.

CPUID The CPUID, or x86 processor identification state, physical register mnemonic format

is of the form CPUID FnXXXX_XXXX_EiX[_xYYY], where XXXX_XXXX is the

hex value in the EAX and YYY is the hex value in ECX.

1.4.4 Register Format

A register is a group of register instances that have the same field format (same bit indices and field names).

1.4.4.1 A Register is a group of Register Instances

All instances of a register:

• Have the same:

• Field bit indices and names

• Field titles, descriptions, valid values.

• Register title

• Register description

• Fields may have different: (instance specific)

• Access Type. See 1.4.4.10 [Field Access Type].

• Reset. See 1.4.4.11 [Field Reset].

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• Init. See 1.4.4.12 [Field Initialization].

• Check. See 1.4.4.13 [Field Check].

1.4.4.2 Register Physical Mnemonic, Title, and Name

A register definition is identified by a table that starts with a heavy bold line. The information above the bold line in order

is:

1. The physical mnemonic of the register.

• A register that has multiple instances, may have instances that have different access methods, each with

it's own physical mnemonic format.

• In the event that there are multiple physical mnemonic formats, the physical mnemonic format chosen is

the most commonly used physical mnemonic.

• The physical mnemonic is not intended to represent the physical mnemonics of all instances of the

find registers by physical mnemonic. If "..." occurs in the physical mnemonic, the range is first ... last.

There is no implication as to how many instances exist between first and last. See 1.4.4.5 [Register

Instance Table].

2. The register title in brackets.

3. The register name in parenthesis.

Figure 7: Register Physical Mnemonic, Title, and Name

1.4.4.3 Full Width Register Attributes

The first line that follows the bold line contains the attributes that apply to all fields of the register. This row is rendered as

a convenience to the reader and replicates content that exists in the register field.

• AccessType: If all non-reserved fields of a register have the same access type, then the access type is rendered in

this row.

• The supported access types are specified by 1.4.4.10 [Field Access Type].

• The example figure shows that the access type "Read-write,Volatile" applies to all non-reserved fields of

the register.

• Reset: If all non-reserved fields of a register have a constant reset and are all the same type (Warm, Cold, Fixed),

then the full width register reset is rendered in this row. The example figure shows the reset

"0000_0000_0000_0000h". See 1.4.4.11 [Field Reset].

• The value zero (0) is assumed for display purposes for all reserved fields.

• If none of the above content is rendered, then this row of the register is not rendered.

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