【免费】WM8960的数据手册_wm8960数据手册,wm8960中文手册

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WM8960

16 Rev 4.4

CONTROL INTERFACE TIMING – 2-WIRE MODE

SDIN

SCLK

Figure 4 Control Interface Timing – 2-Wire Serial Control Mode

Test Conditions

DCVDD=1.8V, DBVDD=AVDD=SPKVDD1=SPKVDD2=3.3V, DGND=AGND=SPKGND1=SPKGND2=0V, T

=+25

C, Slave

Mode, fs=48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.

PARAMETER SYMBOL MIN TYP MAX UNIT

Program Register Input Information

SCLK Frequency

526 kHz

SCLK Low Pulse-Width

1.3 us

SCLK High Pulse-Width

600 ns

Hold Time (Start Condition)

600 ns

Setup Time (Start Condition)

600 ns

Data Setup Time

100 ns

SDIN, SCLK Rise Time

300 ns

SDIN, SCLK Fall Time

300 ns

Setup Time (Stop Condition)

600 ns

Data Hold Time

900 ns

Pulse width of spikes that will be suppressed

0 5 ns

WM8960

Rev 4.4 19

DEVICE DESCRIPTION

INTRODUCTION

The WM8960 is a low power audio CODEC offering a combination of high quality audio, advanced

features, low power and small size. These characteristics make it ideal for portable digital audio

applications with stereo speaker and headphone outputs such as games consoles, portable media

players and multimedia phones.

Stereo class D speaker drivers can provide >1W per channel into 8 loads. BTL configuration

provides high power output and excellent PSRR. Low leakage and pop/click suppression

mechanisms allow direct battery connection, reducing component count and power consumption in

portable battery-powered applications. Highly flexible speaker boost settings provide fully internal

level-shifting of analogue output signals, allowing speaker output power to be maximised while

minimising other analogue supply currents, and requiring no additional components.

A flexible input configuration includes support for two stereo microphone interfaces (single-ended or

pseudo-differential) and additional stereo line inputs. Up to three stereo analogue input sources are

available, removing the need for external analogue switches in many applications. Boost amplifiers

are available for additional gain on the microphone inputs and a programmable gain amplifier with a

mixed signal automatic level control (ALC) keeps the recording volume constant.

The stereo ADC and DAC are of hi-fi quality using a 24-bit, low-order oversampling architecture to

deliver optimum performance. A flexible clocking arrangement supports mixed ADC and DAC sample

rates.

The DAC output signal can be mixed with analogue input signals from the line inputs or bypass paths.

This mix is available on speaker and headphone/line outputs.

The WM8960 has a configurable digital audio interface where ADC data can be read and digital audio

playback data fed to the DAC. It supports a number of audio data formats including I

S, DSP Mode (a

burst mode in which frame sync plus two data packed words are transmitted), MSB-First, left justified

and MSB-First, right justified, and can operate in master or slave modes. In PCM mode A-law and -

law companding is supported.

The SYSCLK (system clock) provides clocking for the ADCs, DACs, DSP core, class D outputs and

the digital audio interface. SYSCLK can be derived directly from the MCLK pin or via an integrated

PLL, providing flexibility to support a wide range of clocking schemes. All MCLK frequencies typically

used in portable systems are supported for sample rates between 8kHz and 48kHz. A flexible

switching clock for the class D speaker drivers (synchronous with the audio DSP clocks for best

performance) is also derived from SYSCLK.

To allow full software control over all its features, the WM8960 uses a 2 wire control interface. It is

fully compatible and an ideal partner for a wide range of industry standard microprocessors,

controllers and DSPs. Unused circuitry can be disabled via software to save power, while low leakage

currents extend standby and off time in portable battery-powered applications.

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