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PLL Performance, Simulation, and Design 2001, Second Edition
Pulse Related Spurs
In classical PLL literature, it is customary to model the reference spurs based entirely on
leakage currents. For older PLLs, where the leakage currents were in the µA range, this made
reasonable estimates for reference spurs and their behavior. However, modern PLLs typically
have leakage currents of 1 nA or less, and therefore other factors tend to dominate the spurs,
except at low comparison frequencies.
Recall that the charge pump comes on for very short periods of time and then is off
during most of the time. It is the length of time that these short charge pump corrections are
made that determines the pulse related spur. In other words, if leakage is not the dominant
factor, then it is this time that the charge pump is on that determines the spur levels. There are
several factors that influence this correction pulse width which include: charge pump
mismatches, unequal transistor turn on times, dead-zone elimination circuitry, and inaccuracies
in the fractional calibration circuitry. Below is an explanation of how these factors can influence
the pulse width.
Mismatch of the charge pump refers to when the sink and source currents of the charge
pump are not properly matched. The higher degree of the mismatch, the wider the correction
pulse of the phase detector becomes. The unequal transistor turn on times refer to when the
PMOS device that sources the current is not matched to the NMOS device that sinks the current.
Since the PMOS process is slower, this typically makes it so that the lowest spur levels actually
do not occur at 0% mismatch, but closer to about 4% mismatch. The dead zone elimination
circuitry is added to keep the PLL out of the dead zone of the phase detector. Around zero phase
error, real world issues of gate delays become a factor. To avoid this problem, circuitry can be
added to ensure that the charge pump comes on for a minimum amount of time, which in turn
impacts spur levels. Inaccuracies in the fractional calibration circuitry can also cause the
fractional spurs to appear. All of these above sources increase the width of the charge pump
correction pulse, so all of these effects contribute to the pulse spur.
For pulse related spur issues, it is important to be aware of the mismatch properties and to
base the design around several different parts to get an idea of the full variations. Mismatch
properties of parts can vary from date code to date code, so it is important to consider that in the
design process. Also, in designs where an op-amp is used in the loop filter, it is best to use all of
the tuning range of the PLL or to center the op-amp around half of the charge pump supply
voltage or slightly higher. Due to this variation of spur level over tuning voltage to the VCO, the
way that spurs are characterized in this chapter are by the worst case spur when the VCO tuning
voltage is varied from 0.5 volts to 0.5 volts below the charge pump supply. The variation can
also be mentioned, since this shows how much the spur varies, but ultimately, the worst case
spur should be the figure of merit. To predict reference spurs caused by the pulsing action of the
charge pump, the following rule applies.
••++++==
Hz1
Fspur
log40GainSpurpurBasePulseSSpurPulse
The reader may be surprised to see that the above formula has the additional Fspur term
added. This was first discovered by making observations with a modulation domain analyzer,
which displays frequency versus time. In the case of the leakage-dominated spur, the VCO
frequency was assumed to be modulated in a sinusoidal manner, which was confirmed with
observations on the bench. However, this was not the case for the pulse-dominated spur. For
these, frequency spikes occur a regular intervals of time corresponding to when the charge pump
turns on. The pulse-dominated spurs were measured and their magnitude could be directly