TI-CC1150.pdf Product Folder Sample

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TI-CC1150.pdf is a comprehensive and detailed document that provides information about the TI-CC1150 product. It includes technical specifications, application notes, reference designs, and other relevant information for the user. The document is organized in a clear and easy-to-navigate format, making it easy for the user to find the information they need. The technical specifications provide detailed information about the device, including its operating frequency, modulation type, and output power. The application notes provide practical guidance on how to use the device in various applications, such as wireless communication and remote control. The reference designs provide examples of how the device can be used in a real-world scenario, providing valuable insights for the user. Overall, the TI-CC1150.pdf is an essential resource for anyone working with the TI-CC1150 product, providing valuable information and guidance for using the device effectively.

Transmit mode

IDLE

Manual freq.

synth. calibration

TX FIFO

underflow

Frequency

synthesizer on

SFSTXON

STX

SFTX

SIDLE

SCAL

IDLE

TXOFF_MODE=00

SRX or STX or SFSTXON

Sleep

SPWD

Crystal

oscillator off

SXOFF

CSn=0

TXOFF_MODE=01

Frequency

synthesizer startup,

optional calibration,

settling

Optional freq.

synth. calibration

Default state when the radio is not

receiving or transmitting. Typ.

current consumption: 1.1 mA.

Lowest power mode.

Current consumption typ

200nA.

All register values are

retained. Typ. current

consumption; 0.22 mA.

Used for calibrating frequency

synthesizer upfront (entering

transmit mode can then be

done quicker). Transitional

state. Typ. current

consumption: 7.7 mA.

Frequency synthesizer is turned on, can optionally be

calibrated, and then settles to the correct frequency.

Transitional state. Typ. current consumption: 7.7 mA.

Frequency synthesizer is on,

ready to start transmitting.

Transmission starts very

quickly after receiving the STX

command strobe.Typ. current

consumption: 7.7 mA.

Typ. current consumption 868 MHz:

14 mA at -10 dBm output,

15 mA at 0 dBm output,

24 mA at +7 dBm output,

29 mA at +10 dBm output.

Optional transitional state. Typ.

current consumption: 7.7 mA.

In FIFO-based modes,

transmission is turned off and

this state entered if the TX

FIFO becomes empty in the

middle of a packet. Typ.

current consumption: 1.1 mA.

CC1150

SWRS037B –JANUARY 2006–REVISED MARCH 2015

www.ti.com

Figure 5-2. Simplified State Diagram with Typical Usage and Current Consumption

5.4 Configuration Software

CC1150 can be configured using the SmartRF Studio [11] software. The SmartRF Studio software is

highly recommended for obtaining optimum register settings, and for evaluating performance and

functionality. A screenshot of the SmartRF Studio user interface for CC1150 is shown in Figure 5-3.

After chip reset, all the registers have default values as shown in the tables in Section 5.20. The optimum

default value therefore needs to be programmed through the SPI interface.

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Product Folder Links: CC1150

A6 A5 A4 A3 A2 A0A1 D

7 D

6 D

5 D

4 D

3 D

2 D

1 D

A6 A5 A4 A3 A2 A0A1

7 D

6 D

5 D

4 D

3 D

2 D

1 D

Read from register:

Write to register:

Hi-Z

SCLK:

CSn:

Hi-Z

X X

Hi-Z

S7 S6 S5 S4 S3 S2 S1 S0

Hi-Z

S7 S6 S5 S4 S3 S2 S1 S0 S7 S6 S5 S4 S3 S2 S1 S0 S7

CC1150

SWRS037B –JANUARY 2006–REVISED MARCH 2015

www.ti.com

Figure 5-4. Configuration Registers Write and Read Operations

Table 5-1. SPI Interface Timing Requirements

PARAMETER DESCRIPTION MIN MAX UNIT

SCLK frequency

— 10

100 ns delay inserted between address byte and data byte (single access), or

between address and data, and between each data byte (burst access).

SCLK frequency, single access

SCLK

MHz

No delay between address and data byte

SCLK frequency, burst access

6.5

No delay between address and data byte, or between data bytes

sp,pd

CSn low to positive edge on SCLK, in power-down mode 150 — µs

CSn low to positive edge on SCLK, in active mode 20 — ns

Clock high 50 — ns

Clock low 50 — ns

rise

Clock rise time — 5 ns

fall

Clock fall time — 5 ns

Setup data (negative SCLK edge) to positive edge on Single access

55 — ns

SCLK

applies between address and data bytes, and Burst access

76 — ns

between data bytes)

Hold data after positive edge on SCLK 20 — ns

Negative edge on SCLK to CSn high 20 — ns

NOTE

The minimum t

sp,pd

figure in Table 5-1 can be used in cases where the user does not read

the CHIP_RDYn signal. CSn low to positive edge on SCLK when the chip is woken from

power-down depends on the start-up time of the crystal being used. The 150 μs in Table 5-1

is the crystal oscillator start-up time measured using crystal AT-41CD2 from NDK.

5.5.1 Chip Status Byte

When the header byte, data byte or command strobe is sent on the SPI interface, the chip status byte is

sent by the CC1150 on the SO pin. The status byte contains key status signals, useful for the MCU. The

first bit, s7, is the CHIP_RDYn signal; this signal must go low before the first positive edge of SCLK. The

CHIP_RDYn signal indicates that the crystal is running and the regulated digital supply voltage is stable.

Bit 6, 5 and 4 comprises the STATE value. This value reflects the state of the chip. The XOSC and power

to the digital core is on in the IDLE state, but all other modules are in power down. The frequency and

channel configuration should only be updated when the chip is in this state. The TX state will be active

when the chip is transmitting.

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