"SN65LVDS047: LVDS发送器功能描述及特性详解"

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The SN65LVDS047 is a high-performance LVDS quad differential line driver designed for use in a wide range of applications. This device, characterized for operation from -40°C to 85°C, features signaling rates of over 400 Mbps (200 MHz), making it ideal for high-speed data transmission requirements. One of the key features of the SN65LVDS047 is its flow-through pinout, which simplifies PCB layout and ensures easy integration into existing designs. The functional block diagram of the device illustrates its four differential input channels (DIN1-DIN4) and corresponding differential output channels (DOUT1-DOUT4), along with enable and power supply connections. The LVDS047 package, marked as LVDS047, offers a compact and robust solution for driving differential signaling over long distances with minimal signal degradation. This makes it suitable for a wide range of applications, including industrial automation, automotive, telecommunications, and more. Overall, the SN65LVDS047 is a versatile and reliable LVDS transmitter that provides high-speed data transmission capabilities in a compact and user-friendly package. Its superior performance, ease of integration, and wide operating temperature range make it a top choice for designers looking for a high-quality solution for their differential line driver needs.

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SWITCHING CHARACTERISTICS

SN65LVDS047

SLLS416B – JUNE 2000 – REVISED DECEMBER 2003

over recommended operating conditions (see

(1)

(2)

and

(3)

)(unless otherwise noted)

TYP

(

PARAMETER TEST CONDITIONS MIN MAX UNIT

PHL

Differential propagation delay, high-to-low 1.4 1.8 2.8 ns

PLH

Differential propagation delay, low-to-high 1.4 1.8 2.8 ns

SK(p)

Differential pulse skew (t

PHLD -

PLHD

), see

(5)

50 300 ps

SK(o)

Channel-to-channel skew, see

(6)

40 300 ps

= 100 Ω ,, C

= 15 pF,

see Figure 2 and Figure 3

SK(pp)

Differential part-to-part skew, see

(7)

1 ns

SK(lim)

Differential part-to-part skew, see

(8)

1.2 ns

Rise time 0.5 1.5 ns

Fall time 0.5 1.5 ns

PHZ

Disable time high to Z 5.5 8 ns

PLZ

Disable time low to Z 5.5 8 ns

= 100 Ω ,, C

= 15 pF,

see Figure 4 and Figure 5

PZH

Enable time Z to high 8.5 12 ns

PZL

Enable time Z to low 8.5 12 ns

(MAX)

Maximum operating frequency, see

(9)

250 MHz

(1) Generator waveform for all tests unless otherwise: f = 1 MHz, Z

= 50 Ω , t

< 1 ns, and t

< 1 ns.

(2) C

includes probe and jig capacitance.

(3) All input voltages are for one channel unless otherwise specified. Other inputs are set to GND.

(4) All typical values are given for: V

= 3.3 V, T

= 25°C.

(5) t

SK(p)

PHL

-t

PLH

| is the magnitude difference in differential propagation delay time between the positive going edge andthe negative going

edge of the same channel.

(6) t

SK(o)

is the differential channel-to-channel skew of any event on the same device.

(7) t

SK(pp)

is the differential part-to-part skew, and is defined as the difference between the minimum and the maximum specified differential

propagation delays. This specification applies to devices at the same V

and within 5°C of each other within the operating temperature

range.

(8) t

SK(lim)

part-to-part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices

over recommended operating temperature and voltage ranges, and across process distribution. t

SK(lim)

is defined as|Min - Max|

differential propagation delay.

(9) f

(MAX)

generator input conditions: t

= t

< 1 ns (0% to 100%), 50% duty cycle, 0 V to 3 V. Output criteria: duty cycle = 45% to55,V

250 mV, all channels switching

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