NXP MFRC523 NFC/射频卡开发指南：完整规格与功能解析

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MFRC523.pdf 是 NXP 官网发布的关于 MFRC523 射频卡/读写器的详细规格文档，这是一款专为13.56MHz接触式通信设计的高性能集成模块。它支持 ISO/IEC 14443A 和 MIFARE 模式，广泛应用于 NFC（近场通信）应用中，如门禁系统、支付终端和智能卡读取等。文档介绍了两种不同的版本： 1. MFRC52302 (HVQFN32)，通常称为 v2.0 版本，与之前的 v1.0 版本相比，可能在功能、性能或兼容性上有改进。 2. MFRC52301 (HVQFN32)，即 v1.0 版本，作为基础型号，提供了基本的读写功能和协议支持。该模块的核心特性包括： - 内置发射器，可以驱动一个无需外部电路即可与 ISO/IEC 14443A 和 MIFARE 协议兼容的卡片及应答器进行通信。 - 高效且可靠的接收模块，能够有效解码并解析来自这些卡片和应答器的信号，执行完整的 ISO/IEC 14443A 帧结构处理和错误检测，包括奇偶校验和循环冗余校验(CRC)。 - 全面支持 ISO/IEC 14443A 和 ISO/IEC 14443B 通信标准的所有协议层，这意味着它可以无缝对接多种卡片类型和应用场景。对于开发者来说，这份文档提供了宝贵的硬件配置指南、接口说明、软件编程接口(SWI)以及典型应用示例，使得设计和实现基于 MFRC523 的射频卡读写系统变得更加容易。无论是初学者还是经验丰富的工程师，都能从中获取必要的技术信息来优化他们的项目设计，并确保系统的稳定性和兼容性。在进行实际项目时，务必查阅其中的差异章节（Section 11），了解不同版本之间的更新和注意事项，以便选择最适合的型号和策略。

Product data sheet

COMPANY PUBLIC

Rev. 4.2 — 27 April 2016

115242 16 of 101

NXP Semiconductors

MFRC523

Standard performance ISO/IEC 14443 A/B frontend

The address byte must meet the following formats:

• the MSB of the first byte sets the mode used

– the MSB is set to logic 0 to write data to the MFRC523

– the MSB is set to logic 1 to read data from the MFRC523

• bit 6 is reserved for future use

• bits [5:0] define the address; see Table 15

8.3.4 I

C Bus Interface

An I

C-bus interface is supported and enables implementation of a low-cost, low pin count

serial bus interface to the host. The I

C-bus interface is implemented based on

NXP Semiconductors’ I

C-bus interface specification, rev. 2.1, January 2000. The

interface can only act in slave mode. Therefore the MFRC523 does not perform clock

generation or access arbitration.

The MFRC523 can act as a slave receiver or slave transmitter in Standard mode, Fast

mode and High-speed mode.

SDA is a bidirectional line connected to a positive supply voltage using a current source or

a pull-up resistor. Both SDA and SCL lines are set HIGH when data is not transmitted. The

MFRC523 has a 3-state output stage to perform the wired-AND function. Data on the

C-bus can be transferred at data rates of up to 100 kBd in Standard mode, up to

400 kBd in Fast mode or up to 3.4 Mbit/s in High-speed mode.

If the I

C-bus interface is selected, spike suppression is activated on lines SCL and SDA

as defined in the I

C-bus interface specification.

See Table 156 on page 79

for timing requirements.

Table 15. Address byte 0 register; address MOSI

Bit 7

(MSB)

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

(LSB)

1 or 0 reserved address address address address address address

Fig 11. I

C-bus interface

001aal160

MFRC523

SDA

SCL

I2C

ADR_[5:0]

PULL-UP

NETWORK

CONFIGURATION

WIRING

PULL-UP

NETWORK

MICROCONTROLLER

Product data sheet

COMPANY PUBLIC

Rev. 4.2 — 27 April 2016

115242 19 of 101

NXP Semiconductors

MFRC523

Standard performance ISO/IEC 14443 A/B frontend

8.3.4.5 7-Bit addressing

During the I

C-bus address procedure, the first byte after the START condition is used to

determine which slave will be selected by the master.

Several address numbers are reserved. During device configuration, the designer must

ensure that collisions with these reserved addresses cannot occur. Check the I

C-bus

specification for a complete list of reserved addresses.

The I

C-bus address specification is dependent on the definition of pin EA. Immediately

after releasing pin NRSTPD or after a power-on reset, the device defines the I

C-bus

address according to pin EA.

If pin EA is set LOW, the upper 4 bits of the device bus address are reserved by

NXP Semiconductors and set to 0101b for all MFRC523 devices. The remaining 3 bits

(ADR_0, ADR_1, ADR_2) of the slave address can be freely configured by the customer

to prevent collisions with other I

C-bus devices.

If pin EA is set HIGH, ADR_0 to ADR_5 can be completely specified at the external pins

according to Table 5 on page 10

. ADR_6 is always set to logic 0.

In both modes, the external address coding is latched immediately after releasing the

reset condition. Further changes at the used pins are not taken into consideration.

Depending on the external wiring, the I

C-bus address pins can be used for test signal

outputs.

8.3.4.6 Register write access

To write data from the host controller using the I

C-bus to a specific register in the

MFRC523 the following frame format must be used.

• The first byte of a frame indicates the device address according to the I

C-bus rules.

• The second byte indicates the register address followed by up to n-data bytes.

In one frame, all data bytes are written to the same register address. This enables fast

FIFO buffer access. The Read/Write (R/W

) bit is set to logic 0.

Fig 16. First byte following the START procedure

001aak591

slave address

bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W

MSB LSB

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