ST25R3912：高性能NFC读卡器与1W输出功率

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"ST25R3912是一款高性能的高频读卡器/NFC启动器，适用于支付应用，可提供1W的输出功率。该器件支持多种标准，包括ISO18092（NFCIP-1）主动P2P、ISO14443A、ISO14443B、ISO15693和FeliCa™。它具备感应唤醒功能，自动调制指数调整，以及AM和PM（I/Q）解调器通道，支持用户可选和自动增益控制。此外，它还能驱动两个单端天线，并兼容不同工作温度范围和电源电压。" 详细说明: ST25R3912是一款专为支付应用设计的高性能NFC（近场通信）发起器/高频读卡器集成电路。它集成了多种功能，使其能够与各种类型的RFID标签和NFC设备进行交互。以下是对这款芯片关键特性的详细解释： 1. **ISO标准支持**：ST25R3912支持多种国际标准，如ISO18092（NFCIP-1）主动点对点模式，允许设备之间直接交换数据；同时，它也兼容ISO14443A、ISO14443B和ISO15693，这使得它可以与众多类型的非接触式智能卡和标签通信。此外，它还支持FeliCa技术，广泛用于日本的电子支付系统。 2. **高比特率通信**：芯片支持高达848kbit/s的高速比特率，这在PICC（无源卡片）到PCD（读卡器）和PCD到PICC的帧结构中是可实现的，提高了数据传输速率。 3. **感应唤醒功能**：ST25R3912具备感应唤醒功能，能在检测到近场信号时自动启动，增强了系统的节能性。 4. **自动调制指数调整**：自动调制指数调整功能确保了与不同RFID设备的最佳通信效果，适应不同条件下的信号强度。 5. **AM和PM解调器**：AM和PM（I/Q）解调器通道可以自动选择，以处理各种调制类型的数据，提高了解码的准确性和效率。 6. **输出功率**：ST25R3912能够提供高达1W的差分输出，适合需要较强发射能力的应用场景。 7. **增益控制**：用户可以选择或自动控制增益，以适应不同的信号环境，确保稳定的数据接收。 8. **多天线驱动**：该芯片能驱动两个单端天线，这在多天线配置中很有用，可以优化天线布局和系统性能。 9. **时钟输入灵活性**：晶振输入支持13.56MHz或27.12MHz的晶体，快速启动，简化了系统设计。 10. **接口**：6Mbit/s SPI接口带有96字节的FIFO，提供了高速数据传输的能力。 11. **电源和温度范围**：宽范围的电源电压（2.4V至5.5V）和工作温度范围（-40°C至125°C），保证了在各种环境下的稳定运行。 12. **封装选项**：ST25R3912提供了VFQFPN32（5mmx5mm）和WLCSP（3.0mmx2.8mm）两种封装形式，适应不同的空间需求。 ST25R3912是一款功能强大的NFC和RFID解决方案，其丰富的特性集和广泛的兼容性使其成为支付应用和其他需要高性能NFC功能的场合的理想选择。

Functional overview ST25R3912

16/130 DS11794 Rev 7

Procedure to implement the slow transition:

1. When transmitter is disabled set IO configuration register 2 bit slow_up to 1. Keep this

state for at least 2 ms to allow discharge of VSP_RF.

2. Enable transmitter, its output will ramp slowly.

3. Before sending any command set the bit slow_up back to 0.

1.2.3 Receiver

The receiver performs demodulation of the transponder sub-carrier modulation that is

superimposed on the 13.56 MHz carrier frequency. It performs AM and/or PM demodulation,

amplification, band-pass filtering and digitalization of sub-carrier signals. Additionally it

performs RSSI measurement, automatic gain control (AGC) and Squelch.

In typical applications the receiver inputs RFI1 and RFI2 are outputs of capacitor dividers

connected directly to the terminals of the antenna coil. This concept ensures that the two

input signals are in phase with the voltage on the antenna coil. The design of the capacitive

divider must ensure that the RFI1 and RFI2 input signal peak values do not exceed the

SP_A

supply voltage level.

The receiver comprises two complete receive channels, one for the AM demodulation and

another one for the PM demodulation. In case both channels are active the selection of the

channel used for reception framing is done automatically by the receive framing logic. The

receiver is switched on when

Operation control register bit rx_en is set to one. Additionally

the Operation control register contains bits rx_chn and rx_man; rx_chn defines whether

both, AM and PM, demodulation channels will be active or only one of them, while bit

rx_man defines the channel selection mode in case both channels are active (automatic or

manual). Operation of the receiver is controlled by four receiver configuration registers.

The operation of the receiver is additionally controlled by the signal rx_on that is set high

when a modulated signal is expected on the receiver input. This signal is used to control

RSSI and AGC and also enables processing of the receiver output by the framing logic.

Signal rx_on is automatically set to high after the Mask Receive Timer expires. Signal rx_on

can also be directly controlled by the controller by sending direct commands Mask Receive

Data and Unmask Receive Data.

Figure 4 details the receiver block diagram.

Functional overview ST25R3912

18/130 DS11794 Rev 7

component. Filtering and gain is implemented in three stages, where the first and the last

stage have first order high pass characteristics, and the second stage has second order low

pass characteristic.

Gain and filtering characteristics can be optimized by writing the Receiver configuration

Receiver configuration register 4 (gain in second and third stage).

The gain of the first stage is about 20 dB and can be reduced in six 2.5 dB steps. There is

also a special boost mode available, which boosts the maximum gain by additional 5.5 dB.

The first stage gain can only be modified by writing

Receiver configuration register 3. The

default setting of this register is the minimum gain. The default first stage zero is set at 60

kHz, it can also be lowered to 40

kHz or to 12 kHz by writing option bits in the Receiver

configuration register 1. The control of the first and third stage zeros is done with common

control bits (see Table 1).

The gain in the second and third stage is 23 dB and can be reduced in six 3 dB steps. The

gain of these two stages is included in the AGC and Squelch loops. It can also be manually

set in

Receiver configuration register 4. Sending of direct command Reset Rx Gain is

necessary to reset the AGC, Squelch and RSSI block. Sending this command clears the

current Squelch setting and loads the gain reduction configuration from

Receiver

configuration register 4 into the internal shadow registers of the AGC and Squelch block.

The second stage has a second order low pass filtering characteristic, the pass band is

adjusted according to the sub-carrier frequency using the bits lp2 to lp0 of the

Receiver

configuration register 1.

See Table 2 for -1 dB cut-off frequency for different settings.

Table 1. First and third stage zero setting

rec1<2> h200 rec1<1> h80 rec1<0> z12k First stage zero Third stage zero

0 0 0 60 kHz 400 kHz

1 0 0 60 kHz 200 kHz

0 1 0 40 kHz 80 kHz

0 0 1 12 kHz 200 kHz

0 1 1 12 kHz 80 kHz

1 0 1 12 kHz 200 kHz

Others Not used

Table 2. Low pass control

rec1<5> lp2 rec1<4> lp1 rec1<3> lp0 -1 dB point

0 0 0 1200 kHz

001600 kHz

010300 kHz

1002 MHz

1017 MHz

Others Not used

DS11794 Rev 7 19/130

ST25R3912 Functional overview

Table 3 provides information on the recommended filter settings. For all supported operation

modes and receive bit rates there is an automatic preset defined, additionally some

alternatives are listed. Automatic preset is done by sending direct command Analog Preset.

There is no automatic preset for Stream and Transparent modes. Since the selection ofthe

filter characteristics also modifies gain, the gain range for different filter settings is also

listed.

Digitizing stage

The digitizing stage produces a digital representation of the sub-carrier signal coming from

the receiver. This digital signal is then processed by the receiver framing logic. The digitizing

stage consists of a window comparator with adjustable digitizing window (five possible

settings, 3 dB steps, adjustment range from ±33 mV to ±120 mV). Adjustment of the

digitizing window is included in the AGC and Squelch loops. In addition, the digitizing

window can also be set manually in the

Receiver configuration register 4.

AGC, Squelch and RSSI

As mentioned above, the second and third gain stage gain and the digitizing stage window

are included in the AGC and Squelch loops. Eleven settings are available. The default state

features minimum digitizer window and maximum gain. The first four steps increase the

digitizer window in 3 dB steps, the next six steps additionally reduce the gain in the second

and third gain stage, again in 3 dB steps. The initial setting with whom Squelch and AGC

start is defined in

Receiver configuration register 4. The Gain reduction state register

displays the actual state of gain that results from Squelch, AGC and initial settings in

Receiver configuration register 4. During bit anticollision like Type A, the AGC should be

disabled.

Table 3. Receiver filter selection and gain range

rec1<5:3>lp<2:0>

rec1<2>h200

rec1<1>h80

rec1<0>z12k

Gain (dB)

Comments

Max

all

Min1

Max23

Max1

Min23

Min

all

With

boost

000 0 0 0 43.4 28.0 26.4 11.0 49.8

Automatic preset for ISO14443A fc / 128 and NFC

Forum Type 1 Tag

000 1 0 0 44.0 29.0 27.5 12.0 49.7

Automatic preset for ISO14443B fc / 128

ISO14443 fc / 64

001 1 0 0 44.3 29 27.0 11.7 49.8 Recommended for 424/484 kHz sub-carrier

000 0 1 0 41.1 25.8 23.6 8.3 46.8 Alternative choice for ISO14443 fc / 32 and fc / 16

100 0 1 0 32.0 17.0 17.2 2.0 37.6 Automatic preset for ISO14443 fc / 32 and fc / 16

000 0 1 1 41.1 25.8 23.6 8.3 46.8

Automatic preset FeliCa

™

(fc / 64, fc / 32)

Alternative choice for ISO14443 fc / 32 and fc / 16

000 1 0 1 36.5 21.5 24.9 9.9 41.5 Automatic preset for NFCIP-1 (initiator and target)

Functional overview ST25R3912

20/130 DS11794 Rev 7

Squelch

This feature is designed for operation of the receiver in noisy conditions. The noise can

come from tags (caused by the processing of reader commands), or it can come from a

noisy environment. This noise may be misinterpreted as start of transponder response,

resulting in decoding errors.

During execution of the Squelch procedure the output of the digitizing comparator is

observed. In case there are more than two transitions on this output in a 50 μs time period,

the receiver gain is reduced by 3 dB, and the output is observed during the next 50 μs. This

procedure is repeated until the number of transitions in 50 μs is lower or equal to two, or

until the maximum gain reduction is reached. This gain reduction can be cleared sending

the direct command Reset Rx Gain.

There are two possibilities of performing squelch: automatic mode and using the direct

command Squelch.

1. Automatic mode is enabled in case bit sqm_dyn in the Receiver configuration register 2

is set. It is activated automatically 18.88 μs after end of Tx and is terminated when the

Mask Receive timer expires. This mode is primarily intended to suppress noise

generated by tag processing during the time when a tag response is not expected

(covered by Mask Receive timer).

2. Command Squelch is accepted in case it is sent when signal rx_on is low. It can be

used when the time window in which noise is present is known by the controller.

AGC (automatic gain control)

AGC is used to reduce gain to keep the receiver chain out of saturation. With gain properly

adjusted the demodulation process is also less influenced by system noise.

AGC action starts when signal rx_on is asserted high and is reset when it is reset to low. At

the high to low transitions of the rx_on signal the state of the receiver gain is stored in the

Gain reduction state register. Reading this register at a later stage gives information on the

gain setting used during last reception.

When AGC is switched on the receiver gain is reduced so that the input to the digitizer stage

is not saturated. The AGC system comprises a comparator with a window 3.5 times larger

than that of the digitizing window comparator. When the AGC function is enabled the gain is

reduced until there are no transitions on the output of its window comparator. This

procedure ensures that the input to the digitizing window comparator is less than 3.5 times

larger than its threshold.

AGC operation is controlled by the control bits agc_en, agc_m and agc_fast in the Receiver

configuration register 2. Bit agc_en enables the AGC operation, bit agc_m defines the AGC

mode, and bit agc_alg defines the AGC algorithm.

Two AGC modes are available. The AGC can operate during the complete Rx process (as

long as signal rx_on is high), or it can be enabled only during the first eight sub-carrier

pulses.

Two AGC algorithms are available. The AGC can either start by presetting code 4h (max

digitizer window, max gain) or by resetting the code to 0h (min digitizer window, max gain).

The algorithm with preset code is faster, therefore it is recommended for protocols with short

SOF (like ISO14443A fc / 128).

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