ATxmega16E5: High-Performance AVR Microcontroller Datasheet

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"ATxmega16E5是Atmel公司基于AVR架构的高性能、低功耗8/16位微控制器。该芯片提供不同容量的非易失性程序和数据存储器，包括8K到32K字节的在系统自编程闪存，2K到4K字节的引导区，512字节到1K字节的EEPROM，以及1K到4K字节的内部SRAM。此外，它还具备丰富的外设功能。" ATxmega16E5是一款集成了多种功能的微控制器，主要特点如下： 1. **高性能、低功耗AVR XMEGA架构**：该微控制器采用了Atmel的AVR XMEGA技术，提供高效的处理能力和低功耗运行，适用于各种嵌入式应用。 2. **内存配置**：其内置的闪存允许用户在系统编程，容量从8K到32K字节不等，方便代码更新和调试。此外，2K到4K字节的引导区用于引导加载程序，而512字节到1K字节的EEPROM则适合存储持久性数据。1K到4K字节的SRAM提供高速数据处理所需的临时存储空间。 3. **外设特性**：ATxmega16E5包含一个四通道增强型DMA控制器，支持8/16位地址匹配，可以高效地传输数据。八通道事件系统和异步同步信号路由提供了灵活的系统集成能力。此外，还包括一个带旋转滤波器的正交编码器，三个16位定时器/计数器，一个带有4个输出比较或输入捕获通道的定时器/计数器，以及两个带有2个输出比较或输入捕获通道的定时器/计数器。 4. **高级定时器功能**：高分辨率扩展提供了高达4ns的PWM分辨率，适用于精确控制电机、LED、照明、H桥和高驱动应用。波形扩展功能进一步增强了这些控制能力。故障扩展功能确保了对外部驱动器的安全和确定性处理或关闭。 5. **CRC模块**：集成的CRC-16 (CRC-CCITT) 和 CRC-32 (IEEE 802.3) 生成器可用于数据完整性检查，是通信和存储应用中的重要工具。 6. **XMEGA Custom Logic (XCL) 模块**：这个模块提供了定时器、计数器和逻辑函数，增强了芯片的灵活性和自定义能力。 7. **8位定时器/计数器**：有两个8位定时器/计数器，具有捕获/比较功能，并支持16位级联模式。这些定时器可以与一个USART接口连接，以支持串行通信。 8. **通信接口**：虽然摘要中没有详细介绍，但通常AVR XMEGA系列微控制器会包含多个USART、SPI和I²C接口，用于与其他设备进行通信。 ATxmega16E5因其丰富的外设集、高效的处理能力和可定制性，在嵌入式设计中广泛应用于各种领域，如工业控制、物联网设备、消费电子产品和自动化系统。通过灵活的外设配置和强大的处理器核心，开发者可以构建复杂而节能的解决方案。

XMEGA E5 [DATASHEET]

8153G–AVR–10/2013

To enable flexibility in transfers, channels can be interlinked so that the second takes over the transfer when the first is

finished.

The EDMA controller supports extended features such as double buffering, data match for peripherals and data search

for SRAM or EEPROM.

The EDMA controller supports two types of channel. Each channel type can be selected individually.

XMEGA E5 [DATASHEET]

8153G–AVR–10/2013

10. Event System

10.1 Features

 System for direct peripheral-to-peripheral communication and signaling

 Peripherals can directly send, receive, and react to peripheral events

 CPU and EDMA controller independent operation

 100% predictable signal timing

 Short and guaranteed response time

 Synchronous and asynchronous event routing

 Eight event channels for up to eight different and parallel signal routing and configurations

 Events can be sent and/or used by most peripherals, clock system, and software

 Additional functions include

 Quadrature decoder with rotary filtering

 Digital filtering of I/O pin state with configurable filter

 Simultaneous synchronous and asynchronous events provided to peripheral

 Works in all sleep modes

10.2 Overview

The event system enables direct peripheral-to-peripheral communication and signaling. It allows a change in one

peripheral’s state to automatically trigger actions in other peripherals. It is designed to provide a predictable system for

short and predictable response times between peripherals. It allows for autonomous peripheral control and interaction

without the use of interrupts, CPU, or EDMA controller resources, and is thus a powerful tool for reducing the complexity,

size and execution time of application code. It allows for synchronized timing of actions in several peripheral modules.

The event system enables also asynchronous event routing for instant actions in peripherals.

A change in a peripheral’s state is referred to as an event, and usually corresponds to the peripheral’s interrupt

conditions. Events can be directly passed to other peripherals using a dedicated routing network called the event routing

network. How events are routed and used by the peripherals is configured in software.

Figure 10-1 shows a basic diagram of all connected peripherals. The event system can directly connect together analog

and digital converters, analog comparators, I/O port pins, the real-time counter, timer/counters, IR communication

module (IRCOM) and XMEGA Custom Logic (programmable logic) block (XCL). It can also be used to trigger EDMA

transactions (EDMA controller). Events can also be generated from software and peripheral clock.

XMEGA E5 [DATASHEET]

8153G–AVR–10/2013

11. System Clock and Clock options

11.1 Features

 Fast start-up time

 Safe run-time clock switching

 Internal Oscillators:

 32MHz run-time calibrated and tuneable oscillator

 8MHz calibrated oscillator with 2MHz output option and fast start-up

 32.768kHz calibrated oscillator

 32kHz Ultra Low Power (ULP) oscillator with 1kHz output

 External clock options

 0.4 - 16MHz Crystal Oscillator

 32kHz crystal oscillator with digital correction

 External clock input in selectable pin location

 PLL with 20 - 128MHz output frequency

 Internal and external clock options and 1 to 31x multiplication

 Lock detector

 Clock Prescalers with 1x to 2048x division

 Fast peripheral clocks running at 2 and 4 times the CPU clock frequency

 Automatic Run-Time Calibration of the 32MHz internal oscillator

 External oscillator and PLL lock failure detection with optional non maskable interrupt

11.2 Overview

Atmel AVR XMEGA E5 devices have a flexible clock system supporting a large number of clock sources. It incorporates

both accurate internal oscillators and external crystal oscillator and resonator support. A high-frequency phase locked

loop (PLL) and clock prescalers can be used to generate a wide range of clock frequencies. A calibration feature (DFLL)

is available, and can be used for automatic run-time calibration of the 32MHz internal oscillator to remove frequency drift

over voltage and temperature. An oscillator failure monitor can be enabled to issue a nonmaskable interrupt and switch

to the internal oscillator if the external oscillator or PLL fails.

When a reset occurs, all clock sources except the 32kHz ultra low power oscillator are disabled. After reset, the device

will always start up running from the 2MHz output of the 8MHz internal oscillator. During normal operation, the system

clock source and prescalers can be changed from software at any time.

Figure 11-1 presents the principal clock system in the XMEGA E5 family of devices. Not all of the clocks need to be

active at a given time. The clocks for the CPU and peripherals can be stopped using sleep modes and power reduction

registers, as described in “Power Management and Sleep Modes” on page 22.

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