"Arduino Mega 2560芯片技术说明文档下载链接"

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ATmega2560 / 640 / 1280 / 1281 / 2561 技术说明文档涵盖了Arduino Mega 2560芯片的详细技术规格和数据表。这些芯片是基于AVR RISC架构的单片机，适用于各种嵌入式系统和电子项目。用户可以通过访问https://www.alldatasheetcn.com/view_datasheet.jsp?sSearchword=ATMEGA2560来下载这些技术说明文档。 Arduino Mega 2560是一款功能强大的开发板，搭载了ATmega2560芯片，提供了丰富的输入输出接口和各种传感器和模块的支持。这款芯片具有高性能、低功耗和丰富的功能特性，适合于各种应用场景。通过详尽的技术说明文档，用户可以了解芯片的架构、指令集、寄存器配置等重要信息，为项目开发和应用提供必要的参考。 ATmega系列芯片具有多种型号，包括ATmega640、ATmega1280、ATmega1281和ATmega2561等，每款芯片都具有自己的特点和应用范围。这些芯片支持各种通信接口、定时器、ADC、PWM等功能模块，可以满足不同项目的需求。因此，用户在选择芯片时需根据具体的项目要求和性能需求来确定最适合的型号。在技术说明文档中，用户可以查找到芯片的引脚定义、电气特性、时钟频率、工作温度范围等详细信息，这些内容对于设计电路、编程程序和调试故障都非常重要。此外，技术说明文档还包括了芯片的仿真模型、应用电路图、软件工具等内容，为用户提供了全面的支持和指导。总的来说，ATmega2560 / 640 / 1280 / 1281 / 2561 技术说明文档为用户提供了全面而详细的信息，帮助用户充分了解和应用这些芯片。无论是初学者还是经验丰富的开发者，都可以从这些技术文档中获取到有用的知识和资料，进而顺利完成项目开发和应用部署。希望用户通过学习和使用这些技术文档，能够更好地利用ATmega系列芯片，创造出更加精彩的电子产品和应用。

ATmega640/1280/1281/2560/2561

2549K–AVR–01/07

Instruction Execution

Timing

This section describes the general access timing concepts for instruction execution. The

AVR CPU is driven by the CPU clock clk

CPU

, directly generated from the selected clock

source for the chip. No internal clock division is used.

Figure 10 shows the parallel instruction fetches and instruction executions enabled by

the Harvard architecture and the fast-access Register File concept. This is the basic

pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results

for functions per cost, functions per clocks, and functions per power-unit.

Figure 10. The Parallel Instruction Fetches and Instruction Executions

Figure 11 shows the internal timing concept for the Register File. In a single clock cycle

an ALU operation using two register operands is executed, and the result is stored back

to the destination register.

Figure 11. Single Cycle ALU Operation

clk

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

2nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

T1 T2 T3 T4

CPU

Total Execution Time

ALU Operation Execute

Result Write Back

T1 T2 T3 T4

clk

CPU

ATmega640/1280/1281/2560/2561

2549K–AVR–01/07

Reset and Interrupt

Handling

The AVR provides several different interrupt sources. These interrupts and the separate

Reset Vector each have a separate program vector in the program memory space. All

interrupts are assigned individual enable bits which must be written logic one together

with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt.

Depending on the Program Counter value, interrupts may be automatically disabled

when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves software

security. See the section “Memory Programming” on page 342 for details.

The lowest addresses in the program memory space are by default defined as the Reset

and Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 69.

The list also determines the priority levels of the different interrupts. The lower the

address the higher is the priority level. RESET has the highest priority, and next is INT0

– the External Interrupt Request 0. The Interrupt Vectors can be moved to the start of

the Boot Flash section by setting the IVSEL bit in the MCU Control Register (MCUCR).

Refer to “Interrupts” on page 69 for more information. The Reset Vector can also be

moved to the start of the Boot Flash section by programming the BOOTRST Fuse, see

“Memory Programming” on page 342.

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts

are disabled. The user software can write logic one to the I-bit to enable nested inter-

rupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is

automatically set when a Return from Interrupt instruction – RETI – is executed.

There are basically two types of interrupts. The first type is triggered by an event that

sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the

actual Interrupt Vector in order to execute the interrupt handling routine, and hardware

clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a

logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the

corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remem-

bered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or

more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the cor-

responding Interrupt Flag(s) will be set and remembered until the Global Interrupt

Enable bit is set, and will then be executed by order of priority.

The second type of interrupts will trigger as long as the interrupt condition is present.

These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disap-

pears before the interrupt is enabled, the interrupt will not be triggered.

When the AVR exits from an interrupt, it will always return to the main program and exe-

cute one more instruction before any pending interrupt is served.

Note that the Status Register is not automatically stored when entering an interrupt rou-

tine, nor restored when returning from an interrupt routine. This must be handled by

software.

When using the CLI instruction to disable interrupts, the interrupts will be immediately

disabled. No interrupt will be executed after the CLI instruction, even if it occurs simulta-

ATmega640/1280/1281/2560/2561

2549K–AVR–01/07

neously with the CLI instruction. The following example shows how this can be used to

avoid interrupts during the timed EEPROM write sequence.

When using the SEI instruction to enable interrupts, the instruction following SEI will be

executed before any pending interrupts, as shown in this example.

Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is five clock cycles

minimum. After five clock cycles the program vector address for the actual interrupt han-

dling routine is executed. During these five clock cycle period, the Program Counter is

pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this

jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle

instruction, this instruction is completed before the interrupt is served. If an interrupt

occurs when the MCU is in sleep mode, the interrupt execution response time is

increased by five clock cycles. This increase comes in addition to the start-up time from

the selected sleep mode.

A return from an interrupt handling routine takes five clock cycles. During these five

clock cycles, the Program Counter (three bytes) is popped back from the Stack, the

Stack Pointer is incremented by three, and the I-bit in SREG is set.

Assembly Code Example

in r16, SREG ; store SREG value

cli ; disable interrupts during timed sequence

sbi EECR, EEMPE ; start EEPROM write

sbi EECR, EEPE

out SREG, r16 ; restore SREG value (I-bit)

C Code Example

char cSREG;

cSREG = SREG; /* store SREG value */

/* disable interrupts during timed sequence */

__disable_interrupt();

EECR |= (1<<EEMPE); /* start EEPROM write */

EECR |= (1<<EEPE);

SREG = cSREG; /* restore SREG value (I-bit) */

Assembly Code Example

sei ; set Global Interrupt Enable

sleep ; enter sleep, waiting for interrupt

; note: will enter sleep before any pending

; interrupt(s)

C Code Example

__enable_interrupt(); /* set Global Interrupt Enable */

__sleep(); /* enter sleep, waiting for interrupt */

/* note: will enter sleep before any pending interrupt(s) */

ATmega640/1280/1281/2560/2561

2549K–AVR–01/07

SRAM Data Memory Table 4 on page 21 shows how the ATmega640/1280/1281/2560/2561 SRAM Memory

is organized.

The ATmega640/1280/1281/2560/2561 is a complex microcontroller with more periph-

eral units than can be supported within the 64 location reserved in the Opcode for the IN

and OUT instructions. For the Extended I/O space from $060 - $1FF in SRAM, only the

ST/STS/STD and LD/LDS/LDD instructions can be used.

The first 4,608/8,704 Data Memory locations address both the Register File, the I/O

Memory, Extended I/O Memory, and the internal data SRAM. The first 32 locations

address the Register file, the next 64 location the standard I/O Memory, then 416 loca-

tions of Extended I/O memory and the next 8,192 locations address the internal data

SRAM.

An optional external data SRAM can be used with the

ATmega640/1280/1281/2560/2561. This SRAM will occupy an area in the remaining

address locations in the 64K address space. This area starts at the address following

the internal SRAM. The Register file, I/O, Extended I/O and Internal SRAM occupies the

lowest 4,608/8,704 bytes, so when using 64KB (65,536 bytes) of External Memory,

60,478/56,832 Bytes of External Memory are available. See “External Memory Inter-

face” on page 26 for details on how to take advantage of the external memory map.

When the addresses accessing the SRAM memory space exceeds the internal data

memory locations, the external data SRAM is accessed using the same instructions as

for the internal data memory access. When the internal data memories are accessed,

the read and write strobe pins (PG0 and PG1) are inactive during the whole access

cycle. External SRAM operation is enabled by setting the SRE bit in the XMCRA

Accessing external SRAM takes one additional clock cycle per byte compared to access

of the internal SRAM. This means that the commands LD, ST, LDS, STS, LDD, STD,

PUSH, and POP take one additional clock cycle. If the Stack is placed in external

SRAM, interrupts, subroutine calls and returns take three clock cycles extra because the

three-byte program counter is pushed and popped, and external memory access does

not take advantage of the internal pipe-line memory access. When external SRAM inter-

face is used with wait-state, one-byte external access takes two, three, or four additional

clock cycles for one, two, and three wait-states respectively. Interrupts, subroutine calls

and returns will need five, seven, or nine clock cycles more than specified in the instruc-

tion set manual for one, two, and three wait-states.

The five different addressing modes for the data memory cover: Direct, Indirect with Dis-

placement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In

the Register file, registers R26 to R31 feature the indirect addressing pointer registers.

The direct addressing reaches the entire data space.

The Indirect with Displacement mode reaches 63 address locations from the base

address given by the Y- or Z-register.

When using register indirect addressing modes with automatic pre-decrement and post-

increment, the address registers X, Y, and Z are decremented or incremented.

The 32 general purpose working registers, 64 I/O registers, and the 4,196/8,192 bytes of

internal data SRAM in the ATmega640/1280/1281/2560/2561 are all accessible through

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