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首页Allwinner A10 用户手册:Cortex-A8处理器与Mali-400 GPU详解
Allwinner A10 用户手册:Cortex-A8处理器与Mali-400 GPU详解
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更新于2024-07-26
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"全志A10 User Manual 是一份由全志科技公司编写的用户手册,专注于介绍A10芯片的使用方法,包括其寄存器的详细操作指南。该手册适用于那些需要深入理解A10芯片硬件特性和进行系统级编程的开发者。A10芯片基于ARM Cortex-A8架构,集成Mali-400图形处理器,并支持SDRAM内存以及各种功能如PWM等。"
全志A10芯片是一款基于ARM Cortex-A8内核的处理器,设计用于高性能、低功耗的应用场景。Cortex-A8是ARM公司推出的32位微处理器核心,遵循ARMv7指令集,广泛应用于移动设备和嵌入式系统中,提供了良好的计算性能与能效比。
Mali-400是ARM Holdings开发的2D/3D图形处理器单元,它为A10提供了图形渲染能力,支持高清视频播放和复杂的图形界面,对于运行图形密集型应用或操作系统至关重要,例如Android、Linux等。
SDRAM(Synchronous Dynamic Random Access Memory)是一种同步动态随机访问内存,与系统总线同步工作,提供快速的数据读写速度,是现代计算机和电子设备中常见的内存类型。在A10芯片中,SDRAM用于存储操作系统、应用程序和其他运行时数据。
PWM(Pulse Width Modulation)是一种模拟信号输出技术,通过改变脉冲宽度来调整输出电压的平均值,常用于控制电源管理、电机速度调节、LED亮度控制等多种用途。A10芯片内置的PWM模块使得开发者可以精确地管理这些功能。
此外,该手册的修订历史显示,自2011年8月的初始版本以来,经过多次更新,特别是在音频编解码器和USB方面的描述有所改进,表明全志科技在不断优化A10的文档,以提供更准确和全面的技术支持。
全志A10 User Manual 是一款深入介绍A10芯片的参考资料,涵盖了其核心组件、内存系统以及关键外设接口的详细信息,对于硬件开发者和系统集成者来说,是理解和利用A10芯片功能的关键工具。
For WITS Only
Allwinner Technology CO., Ltd. A10
A10 User Manual V1.20
Copyright © 2011-2012 Allwinner Technology. All Rights Reserved. 15
2012-04-09
30.3.18. PB Pull Register 1 .................................................................................................................. 298
30.3.19. PC Configure Register 0 ........................................................................................................ 298
30.3.20. PC Configure Register 1 ........................................................................................................ 299
30.3.21. PC Configure Register 2 ........................................................................................................ 301
30.3.22. PC Configure Register 3 ........................................................................................................ 302
30.3.23. PC Data Register .................................................................................................................... 302
30.3.24. PC Multi-Driving Register 0 .................................................................................................. 303
30.3.25. PC Multi-Driving Register 1 .................................................................................................. 303
30.3.26. PC Pull Register 0 .................................................................................................................. 303
30.3.27. PC Pull Register 1 .................................................................................................................. 303
30.3.28. PD Configure Register 0 ........................................................................................................ 304
30.3.29. PD Configure Register 1 ........................................................................................................ 305
30.3.30. PD Configure Register 2 ........................................................................................................ 306
30.3.31. PD Configure Register 3 ........................................................................................................ 307
30.3.32. PD Data Register .................................................................................................................... 308
30.3.33. PD Multi-Driving Register 0 .................................................................................................. 309
30.3.34. PD Multi-Driving Register 1 .................................................................................................. 309
30.3.35. PD Pull Register 0 .................................................................................................................. 309
30.3.36. PD Pull Register 1 .................................................................................................................. 309
30.3.37. PE Configure Register 0 ......................................................................................................... 310
30.3.38. PE Configure Register 1 ......................................................................................................... 311
30.3.39. PE Configure Register 2 ......................................................................................................... 312
30.3.40. PE Configure Register 3 ......................................................................................................... 312
30.3.41. PE Data Register .................................................................................................................... 312
30.3.42. PE Multi-Driving Register 0 .................................................................................................. 312
30.3.43. PE Multi-Driving Register 1 .................................................................................................. 313
30.3.44. PE Pull Register 0 .................................................................................................................. 313
30.3.45. PE Pull Register 1 .................................................................................................................. 313
30.3.46. PF Configure Register 0 ......................................................................................................... 313
30.3.47. PF Configure Register 1 ......................................................................................................... 314
30.3.48. PF Configure Register 2 ......................................................................................................... 314
30.3.49. PF Configure Register 3 ......................................................................................................... 315
30.3.50. PF Data Register .................................................................................................................... 315
30.3.51. PF Multi-Driving Register 0 .................................................................................................. 315
30.3.52. PF Multi-Driving Register 1 .................................................................................................. 315
30.3.53. PF Pull Register 0................................................................................................................... 316
30.3.54. PF Pull Register 1................................................................................................................... 316
30.3.55. PG Configure Register 0 ........................................................................................................ 316
30.3.56. PG Configure Register 1 ........................................................................................................ 317
30.3.57. PG Configure Register 2 ........................................................................................................ 318
30.3.58. PG Configure Register 3 ........................................................................................................ 318
30.3.59. PG Data Register .................................................................................................................... 318
30.3.60. PG Multi-Driving Register 0 .................................................................................................. 319
30.3.61. PG Multi-Driving Register 1 .................................................................................................. 319
For WITS Only
Allwinner Technology CO., Ltd. A10
A10 User Manual V1.20
Copyright © 2011-2012 Allwinner Technology. All Rights Reserved. 16
2012-04-09
30.3.62. PG Pull Register 0 .................................................................................................................. 319
30.3.63. PG Pull Register 1 .................................................................................................................. 319
30.3.64. PH Configure Register 0 ........................................................................................................ 320
30.3.65. PH Configure Register 1 ........................................................................................................ 321
30.3.66. PH Configure Register 2 ........................................................................................................ 322
30.3.67. PH Configure Register 3 ........................................................................................................ 323
30.3.68. PH Data Register .................................................................................................................... 324
30.3.69. PH Multi-Driving Register 0 .................................................................................................. 325
30.3.70. PH Multi-Driving Register 1 .................................................................................................. 325
30.3.71. PH Pull Register 0 .................................................................................................................. 325
30.3.72. PH Pull Register 1 .................................................................................................................. 325
30.3.73. PI Configure Register 0 .......................................................................................................... 326
30.3.74. PI Configure Register 1 .......................................................................................................... 327
30.3.75. PI Configure Register 2 .......................................................................................................... 328
30.3.76. PI Configure Register 3 .......................................................................................................... 329
30.3.77. PI Data Register ..................................................................................................................... 329
30.3.78. PI Multi-Driving Register 0 ................................................................................................... 330
30.3.79. PI Multi-Driving Register 1 ................................................................................................... 330
30.3.80. PI Pull Register 0 ................................................................................................................... 330
30.3.81. PI Pull Register 1 ................................................................................................................... 330
30.3.82. PIO Interrupt Configure Register 0 ........................................................................................ 331
30.3.83. PIO Interrupt Configure Register 1 ........................................................................................ 331
30.3.84. PIO Interrupt Configure Register 2 ........................................................................................ 331
30.3.85. PIO Interrupt Configure Register 3 ........................................................................................ 332
30.3.86. PIO Interrupt Control Register ............................................................................................... 332
30.3.87. PIO Interrupt Status Register ................................................................................................. 332
30.3.88. PIO Interrupt Debounce Register ........................................................................................... 333
31. CSI0 with ISP FE ................................................................................................................................. 334
31.1. Overview ........................................................................................................................................ 334
31.2. Feature ............................................................................................................................................ 334
31.2.1. CSI ......................................................................................................................................... 334
31.2.2. ISP FE .................................................................................................................................... 334
31.3. Block diagram ................................................................................................................................ 335
31.3.1. CSI data ports ......................................................................................................................... 335
31.4. Timing ............................................................................................................................................ 335
31.4.1. CSI timing .............................................................................................................................. 335
31.4.2. 16bit YUV422 Timing ........................................................................................................... 336
31.4.3. CCIR656 2 channel Timing ................................................................................................... 336
31.4.4. CCIR656 4 channel Timing ................................................................................................... 337
31.4.5. CCIR656 Header Code .......................................................................................................... 337
31.5. CSI0 Register List .......................................................................................................................... 338
For WITS Only
Allwinner Technology CO., Ltd. A10
A10 User Manual V1.20
Copyright © 2011-2012 Allwinner Technology. All Rights Reserved. 17
2012-04-09
31.6. CSI0 Register Description.............................................................................................................. 343
31.6.1. CSI Enable Register ............................................................................................................... 343
31.6.2. CSI configuration register ...................................................................................................... 343
31.6.3. CSI capture control register ................................................................................................... 345
31.6.4. CSI horizontal scale register .................................................................................................. 346
31.6.5. CSI Channel_0 FIFO 0 output buffer-A address register ....................................................... 346
31.6.6. CSI Channel_0 FIFO 0 output buffer-B address register ....................................................... 346
31.6.7. CSI Channel_0 FIFO 1 output buffer-A address register ....................................................... 347
31.6.8. CSI Channel_0 FIFO 1 output buffer-B address register ....................................................... 347
31.6.9. CSI Channel_0 FIFO 2 output buffer-A address register ....................................................... 347
31.6.10. CSI Channel_0 FIFO 2 output buffer-B address register ....................................................... 347
31.6.11. CSI Channel_0 output buffer control register ........................................................................ 347
31.6.12. CSI Channel_0 status register ................................................................................................ 348
31.6.13. CSI Channel_0 interrupt enable register ................................................................................ 349
31.6.14. CSI Channel_0 interrupt status register ................................................................................. 350
31.6.15. CSI Channel_0 horizontal size register .................................................................................. 350
31.6.16. CSI Channel_0 vertical size register ...................................................................................... 350
31.6.17. CSI Channel_0 buffer length register ..................................................................................... 351
31.6.18. CSI Channel_1 FIFO 0 output buffer-A address register ....................................................... 351
31.6.19. CSI Channel_1 FIFO 0 output buffer-B address register ....................................................... 351
31.6.20. CSI Channel_1 FIFO 1 output buffer-A address register ....................................................... 351
31.6.21. CSI Channel_1 FIFO 1 output buffer-B address register ....................................................... 352
31.6.22. CSI Channel_1 FIFO 2 output buffer-A address register ....................................................... 352
31.6.23. CSI Channel_1 FIFO 2 output buffer-B address register ....................................................... 352
31.6.24. CSI Channel_1 output buffer control register ........................................................................ 352
31.6.25. CSI Channel_1 status register ................................................................................................ 353
31.6.26. CSI Channel_1 interrupt enable register ................................................................................ 353
31.6.27. CSI Channel_1 interrupt status register ................................................................................. 354
31.6.28. CSI Channel_1 horizontal size register .................................................................................. 355
31.6.29. CSI Channel_1 vertical size register ...................................................................................... 355
31.6.30. CSI Channel_1 buffer length register ..................................................................................... 356
31.6.31. CSI Channel_2 FIFO 0 output buffer-A address register ....................................................... 356
31.6.32. CSI Channel_2 FIFO 0 output buffer-B address register ....................................................... 356
31.6.33. CSI Channel_2 FIFO 1 output buffer-A address register ....................................................... 356
31.6.34. CSI Channel_2 FIFO 1 output buffer-B address register ....................................................... 356
31.6.35. CSI Channel_2 FIFO 2 output buffer-A address register ....................................................... 357
31.6.36. CSI Channel_2 FIFO 2 output buffer-B address register ....................................................... 357
31.6.37. CSI Channel_2 output buffer control register ........................................................................ 357
31.6.38. CSI Channel_2 status register ................................................................................................ 358
31.6.39. CSI Channel_2 interrupt enable register ................................................................................ 358
31.6.40. CSI Channel_2 interrupt status register ................................................................................. 359
31.6.41. CSI Channel_2 horizontal size register .................................................................................. 360
31.6.42. CSI Channel_2 vertical size register ...................................................................................... 360
31.6.43. CSI Channel_2 buffer length register ..................................................................................... 360
For WITS Only
Allwinner Technology CO., Ltd. A10
A10 User Manual V1.20
Copyright © 2011-2012 Allwinner Technology. All Rights Reserved. 18
2012-04-09
31.6.44. CSI Channel_3 FIFO 0 output buffer-A address register ....................................................... 361
31.6.45. CSI Channel_3 FIFO 0 output buffer-B address register ....................................................... 361
31.6.46. CSI Channel_3 FIFO 1 output buffer-A address register ....................................................... 361
31.6.47. CSI Channel_3 FIFO 1 output buffer-B address register ....................................................... 361
31.6.48. CSI Channel_3 FIFO 2 output buffer-A address register ....................................................... 361
31.6.49. CSI Channel_3 FIFO 2 output buffer-B address register ....................................................... 362
31.6.50. CSI Channel_3 output buffer control register ........................................................................ 362
31.6.51. CSI Channel_3 status register ................................................................................................ 362
31.6.52. CSI Channel_3 interrupt enable register ................................................................................ 363
31.6.53. CSI Channel_3 interrupt status register ................................................................................. 364
31.6.54. CSI Channel_3 horizontal size register .................................................................................. 364
31.6.55. CSI Channel_3 vertical size register ...................................................................................... 365
31.6.56. CSI Channel_3 buffer length register ..................................................................................... 365
31.6.57. ISP Enable register ................................................................................................................. 365
31.6.58. ISP Mode register ................................................................................................................... 366
31.6.59. ISP OBC Image Black size register........................................................................................ 367
31.6.60. ISP OBC Image Valid size register ........................................................................................ 367
31.6.61. ISP OBC Image Start register................................................................................................. 367
31.6.62. ISP OBC configuration register ............................................................................................. 368
31.6.63. ISP Horizontal OBC window start register ............................................................................ 368
31.6.64. ISP Vertical OBC window start register ................................................................................. 369
31.6.65. ISP Vertical OBC parameter register ...................................................................................... 369
31.6.66. ISP OBC fixed value register ................................................................................................. 369
31.6.67. ISP OBC offset register .......................................................................................................... 370
31.6.68. ISP OBC clamp value register ................................................................................................ 370
31.6.69. ISP LSC configuration register .............................................................................................. 370
31.6.70. ISP LSC gain factor address register ...................................................................................... 371
31.6.71. ISP LSC gain factor address length register ........................................................................... 371
31.6.72. ISP Offset register .................................................................................................................. 371
31.6.73. ISP Gain Factor register ......................................................................................................... 371
31.6.74. ISP Dark Frame Enable register ............................................................................................. 372
31.6.75. ISP Dark Frame buffer address register ................................................................................. 372
31.6.76. ISP Dark Frame buffer address length register ...................................................................... 372
31.6.77. ISP luma DC subtraction value register ................................................................................. 373
31.6.78. ISP H3A Median filter threshold register ............................................................................... 373
31.6.79. ISP AF window number register ............................................................................................ 373
31.6.80. ISP AF window size register .................................................................................................. 374
31.6.81. ISP AF window start register.................................................................................................. 374
31.6.82. ISP AF configuration register ................................................................................................. 374
31.6.83. ISP AF filter parameter 0 register ........................................................................................... 375
31.6.84. ISP AF filter parameter 1 register ........................................................................................... 375
31.6.85. ISP AF filter parameter 2 register ........................................................................................... 375
31.6.86. ISP AWBE window number register ...................................................................................... 376
31.6.87. ISP AWBE window size register ............................................................................................ 376
For WITS Only
Allwinner Technology CO., Ltd. A10
A10 User Manual V1.20
Copyright © 2011-2012 Allwinner Technology. All Rights Reserved. 19
2012-04-09
31.6.88. ISP AWBE window start register ........................................................................................... 376
31.6.89. ISP AWBE configuration register .......................................................................................... 377
31.6.90. ISP Histogram region 0 window size register ........................................................................ 377
31.6.91. ISP Histogram region 0 window start register ....................................................................... 377
31.6.92. ISP Histogram region 1 window size register ........................................................................ 378
31.6.93. ISP Histogram region 1 window start register ....................................................................... 378
31.6.94. ISP Histogram region 2 window size register ........................................................................ 378
31.6.95. ISP Histogram region 2 window start register ....................................................................... 379
31.6.96. ISP Histogram region 3 window size register ........................................................................ 379
31.6.97. ISP Histogram region 3 window start register ....................................................................... 379
31.6.98. ISP 3A Statistics output address register ................................................................................ 380
31.6.99. ISP LUT Defect Correction configuration register ................................................................ 380
31.6.100. ISP LUT Defect Correction address register .......................................................................... 380
31.6.101. ISP FE Y/Raw Output address length register ....................................................................... 381
31.6.102. SP FE Y/Raw Output address register .................................................................................... 381
31.6.103. ISP interrupt enable register ................................................................................................... 381
31.6.104. ISP interrupt status register .................................................................................................... 382
31.6.105. ISP FE CbCr Output address length register .......................................................................... 382
31.6.106. ISP FE CbCr Output address register ..................................................................................... 383
32. CSI1 ....................................................................................................................................................... 384
32.1. Overview ........................................................................................................................................ 384
32.2. Block diagram ................................................................................................................................ 384
32.3. CSI data ports ................................................................................................................................. 385
32.4. Timing ............................................................................................................................................ 385
32.4.1. CSI timing .............................................................................................................................. 385
32.5. CSI1 Registers List ........................................................................................................................ 385
32.6. CSI1 Register Description.............................................................................................................. 386
32.6.1. CSI Enable Register ............................................................................................................... 386
32.6.2. CSI configuration register ...................................................................................................... 387
32.6.3. CSI capture control register ................................................................................................... 389
32.6.4. CSI horizontal scale register .................................................................................................. 389
32.6.5. CSI Channel_0 FIFO 0 output buffer-A address register ....................................................... 390
32.6.6. CSI Channel_0 FIFO 0 output buffer-B address register ....................................................... 390
32.6.7. CSI Channel_0 FIFO 1 output buffer-A address register ....................................................... 390
32.6.8. CSI Channel_0 FIFO 1 output buffer-B address register ....................................................... 391
32.6.9. CSI Channel_0 FIFO 2 output buffer-A address register ....................................................... 391
32.6.10. CSI Channel_0 FIFO 2 output buffer-B address register ....................................................... 391
32.6.11. CSI Channel_0 output buffer control register ........................................................................ 391
32.6.12. CSI Channel_0 status register ................................................................................................ 392
32.6.13. CSI Channel_0 interrupt enable register ................................................................................ 393
32.6.14. CSI Channel_0 interrupt status register ................................................................................. 394
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