ModelSim SE仿真教程：使用脚本语言do文件

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"ModelSim SE Reference Manual 是一份关于如何使用脚本语言（主要指TCL）在ModelSim SE环境下进行仿真的详细指南。该手册涵盖了软件版本10.1a的相关内容，由Mentor Graphics公司发布并拥有版权。手册允许原始接收者在内部业务目的下复制整份或部分内容，但必须保留所有副本中的版权通知，并同意防止未经授权的使用和分布。 ModelSim是一款强大的硬件描述语言(HDL)仿真器，支持VHDL、Verilog以及SystemVerilog等标准。SE版本是其标准版，提供了一套全面的工具集用于设计验证和仿真。该参考手册旨在为用户提供信息和指导，帮助他们理解并运用ModelSim SE的特性。在ModelSim中，TCL（Tool Command Language）被广泛用于自动化任务，如设置仿真环境、编译设计、运行测试 bench、控制仿真流程以及分析结果。通过编写.do文件，用户可以创建自定义的脚本来简化和优化他们的仿真工作流程。手册可能会详细介绍以下内容： 1. ModelSim SE的安装与启动：包括系统要求、安装步骤及首次使用时的配置。 2. 工作环境：界面介绍、项目管理、工程设置等。 3. 设计编译：如何导入HDL文件、设置编译命令及库管理。 4. TCL基础：TCL语法、变量、控制结构、函数等，以便编写仿真脚本。 5. 仿真控制：启动仿真、设置时间窗口、控制仿真步进、处理信号值等。 6. 测试 bench操作：创建和运行测试 bench，包括激励生成、断点设置、波形查看等。 7. 分析结果：查看波形、提取数据、使用图形化工具进行结果分析。 8. 错误处理与调试：理解错误消息、调试技巧和问题解决方法。请注意，虽然手册提供了详尽的信息，但Mentor Graphics有权随时更改产品规格和信息，且不会提前通知。因此，用户在使用时应始终参考最新版本的手册或直接咨询Mentor Graphics以获取最新的更新。此外，手册中的任何事实陈述或性能表示都不构成保修或保证，Mentor Graphics的产品销售和许可条件都写入了与客户之间的书面协议中。这意味着，除非有明确的书面约定，否则用户不应依赖手册中的任何表述作为产品性能的依据。 ModelSim SE Reference Manual 是一个宝贵的资源，对于需要在ModelSim SE环境中使用TCL脚本进行HDL仿真的工程师来说，它提供了必要的指南和工具，以提高设计验证的效率和准确性。"

ModelSim SE Reference Manual, v10.1a

Syntax and Conventions

File and Directory Pathnames

Several ModelSim commands have arguments that point to files or directories. For example, the

-y argument to vlog specifies the Verilog source library directory to search for undefined

modules. Spaces in file pathnames must be escaped or the entire path must be enclosed in

quotes. For example:

vlog top.v -y C:/Documents\ and\ Settings/projects/dut

vlog top.v -y "C:/Documents and Settings/projects/dut"

Design Object Names

Design objects are organized hierarchically. Each of the following objects creates a new level in

the hierarchy:

• VHDL — component instantiation statement, block statement, and package

• Verilog — module instantiation, named fork, named begin, task and function

• SystemVerilog — class, package, program, and interface

• SystemC — module instantiation

Object Name Syntax

The syntax for specifying object names in ModelSim is as follows:

[<dataset_name><datasetSeparator>][<pathSeparator>][<hierarchicalPath>]

<objectName>[<elementSelection>]

where

• dataset_name — is the name mapped to the WLF file in which the object exists. The

currently active simulation is the “sim” dataset. Any loaded WLF file is referred to by

the logical name specified when the WLF file was loaded. Refer to the chapter

“Recording Simulation Results With Datasets” in the User’s Manual for more

information.

• datasetSeparator — is the character used to terminate the dataset name. The default is

colon ( : ), though a different character (other than backslash ( \ )) may be specified as

the dataset separator via the DatasetSeparator variable in the modelsim.ini file. This

character must be different than the pathSeparator character.

• pathSeparator — is the character used to separate hierarchical object names. Normally,

a backslash ( \ ) is used for VHDL and a period ( . ) is used for Verilog, although other

characters (except a backslash ( \ )) may be specified via the PathSeparator variable in

Syntax and Conventions

Design Object Names

ModelSim SE Reference Manual, v10.1a

the modelsim.ini file. This character must be different than the datasetSeparator. Both

( . ) and forward slash ( / ) can be used for SystemC. Neither ( . ) nor ( / ) can be used

when referring to the contents of a SystemVerilog package or class.

• hierarchicalPath — is a set of hierarchical instance names separated by a path

separator and ending in a path separator prior to the objectName. For example,

/top/proc/clk.

• objectName — is the name of an object in a design.

• elementSelection — indicates some combination of the following:

o Array indexing — Single array elements are specified using either parentheses ( () )

or square brackets ( [] ) around a single number. You must also surround the object

and specified array element with curly braces ( {} ). Refer to Tcl Syntax and

Specification of Array Bits and Slices for important information about using square

brackets and parentheses in ModelSim commands.

o Array slicing — Slices (or part-selects) of arrays are specified using either

parentheses ( () ) or square brackets ( [] ) around a range specification. A range is

two numbers separated by one of the following: " to ", " downto ", or a colon ( : ).

You must also surround the object and specified array slice with curly braces ( {} ).

Refer to Tcl Syntax and Specification of Array Bits and Slices for important

information about using square brackets and parentheses in ModelSim commands.

o Record field selection — A record field is specified using a period ( . ) followed by

the name of the field.

o C++ class, structure, and union member selection — A class, structure, or union

member is specified using the record field specification syntax, described just above.

Tcl Syntax and Specification of Array Bits and Slices

Because ModelSim is a Tcl-based tool, you must surround objects and signals with curly braces

( {} ) when specifying array bits or slices with parentheses ( () ), spaces, or square brackets

( [] ). For example:

toggle add {data[3:0]}

toggle add {data(3 to 0)}

force {bus1[1]} 1

Further Details

Because ModelSim is basd on Tcl, its commands follow Tcl syntax. One problem you may

encounter with ModelSim commands is the use of square brackets ( [] ), parentheses ( () ), or

spaces when specifying array bits and slices. As shown on the previous page, square brackets

are used to specify slices of arrays (for example, data[3:0]). However, in Tcl, square brackets

signify command substitution. Consider the following example:

ModelSim SE Reference Manual, v10.1a

Syntax and Conventions

Design Object Names

examine myPackage::packet::a(0)

examine /top/my.a(0)

Both of the above commands return the contents of the first element of the static array a

within class packet.

examine /top/my.b

Return the contents of the instance-specific array b.

examine /top/my.b(0)

Return the contents of the first element of the instance-specific array b.

When referring to the contents of a package or class, you cannot use the standard path

separators, a period ( . ) or a forward slash ( / ).

Specifying Names

We distinguish between four "types" of object names: simple, relative, fully-rooted, and

absolute.

• Simple name — does not contain any hierarchy. It is simply the name of an object (e.g.,

clk or data[3:0]) in the current context.

• Relative name — does not start with a path separator and may or may not include a

dataset name or a hierarchical path (e.g., u1/data or view:clk). A relative name is relative

to the current context in the current or specified dataset.

• Fully-rooted name — starts with a path separator and includes a hierarchical path to an

object (e.g., /top/u1/clk).There is a special case of a fully-rooted name where the top-

level design unit name can be unspecified (e.g., /u1/clk). In this case, the first top-level

instance in the design is assumed.

• Absolute name — is an exactly specified hierarchical name containing a dataset name

and a fully rooted name (e.g., sim:/top/u1/clk).

The current dataset is used when accessing objects where a dataset name is not specified as part

of the name. The current dataset is determined by the dataset currently selected in the Structure

window or by the last dataset specified in an environment.

The current context in the current or specified dataset is used when accessing objects with

relative or simple names. The current context is either the current process, if any, or the current

instance if there is no current process, or the current process is not in the current instance. The

situation of the current process not being in the current instance can occur, for example, by

selecting a different instance in the Structure tab or by using the environment to set the current

context to a different instance.

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