STM32L5单片机高性能编程指南：Cortex-M33特性与应用

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本指南是针对STM32L5和STM32U5系列单片机的编程手册，特别关注于STM32 Cortex-M33处理器的开发。它详尽地介绍了这款高性能32位微控制器的编程模型、指令集以及核心外设，旨在为应用级和系统级软件开发者提供全面的指导。首先，Cortex-M33处理器以其卓越的性能和快速中断处理能力脱颖而出。它的设计专注于微控制器和微处理器市场，能够满足高效能和实时响应的需求。其强大的处理能力结合了高效的指令执行，使得信号处理应用程序有了更高的处理效率。在调试方面，该处理器提供了丰富的断点和跟踪功能，使开发者能够深入分析代码执行过程，轻松定位和解决问题。这极大地提升了软件开发的便利性和准确性。为了优化能源消耗，Cortex-M33内嵌了多种睡眠模式，能够在保持低功耗的同时满足临时的计算需求。这对于能源敏感的应用场景，如物联网设备或电池供电设备来说，是一项重要的特性。安全性也是该处理器的一大亮点，集成的内存保护单元确保了系统的稳定性，而Security Extension for Armv8-M则提供了额外的安全措施，保护数据和程序免受恶意攻击。适用的产品系列包括STM32L5和STM32U5，覆盖了这些系列中的微控制器型号。这份文档是PM0264版本的编程手册，修订版发布于2022年3月，包含了最新的技术细节和更新内容。对于希望利用STM32L5单片机进行开发的工程师来说，阅读这份手册是至关重要的，它不仅提供了硬件配置和驱动程序信息，还包含了示例代码、API文档以及故障排除策略，帮助开发者充分利用这些先进设备的潜力，实现高效、可靠和安全的系统设计。

Table 14. FAULTMASK register bit assignments

Bits Name Function

[31:1] - Reserved, res0

[0] FM

When TrustZone is disabled, setting this bit to one boosts the current execution priority to -1, masking all

exceptions except NMI.

When TrustZone is enabled, setting this bit to one boosts the current execution priority to -1, masking all

exceptions with a lower priority. If

AIRCR.BFHFNMINS is:

Setting FAULTMASK_S to one boosts the current execution priority to -1.

If AIRCR.PRIS is:

0: Setting FAULTMASK_NS to one boosts the current execution priority to 0

1: Setting FAULTMASK_NS to one boosts the current execution priority to 80

Setting FAULTMASK_S to one boosts the current execution priority to -3.

Setting FAULTMASK_NS to one boosts the current execution priority to -1.

When the current execution priority is boosted to a particular value, all exceptions with a lower or equal

priority are masked.

2.1.3.7.3 Base Priority Mask Register

Use the BASEPRI register to change the priority level that is required for exception preemption.

See Table 2. Core register set summary without the Security Extension table for the BASEPRI register attributes.

The bit assignments for the BASEPRI register are as follows:

BASEPRI

RES0

31 078

Table 15. BASEPRI register bit assignments

Bits Name Function

[31:8] - Reserved, res0

[7:0]

BASEPRI

(1)

Software can set BASEPRI to a priority number between 1 and the maximum supported priority number.

Software can set BASEPRI_S to a priority number between 1 and the maximum supported priority

number. If AIRCR.PRIS is:

Software can set BASEPRI_NS to a priority number between 1 and the

maximum supported priority number.

Software can set BASEPRI_NS to a priority number between 1 and the

maximum supported priority number. The value in BASEPRI_NS is then

mapped to the bottom half of the priority range, so that the current execution

priority is boosted to the mapped-to value in the bottom half of the priority

range.

When the current execution priority is boosted to a particular value, all exceptions with a lower priority

are masked. Writing 0 to BASEPRI disables base priority boosting.

1. This field is similar to the priority fields in the interrupt priority registers. If the device implements only bits[7:M] of this field,

bits[M-1:0] read as zero and ignore writes. See Section 4.2.7 Interrupt Priority Registers for more information. Remember

that higher priority field values correspond to lower exception priorities.

2.1.3.8 CONTROL register

The CONTROL register controls the stack that is used, the privilege level for software execution when the core is

in Thread mode and indicates whether the FPU state is active.

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See Table 2. Core register set summary without the Security Extension table for the CONTROL register attributes.

This register is banked between Security states on a bit by bit basis.

The bit assignments for the CONTROL register are as follows:

31 2 1 0

RES0

SPSEL

FPCA

nPRIV

SFPA

Table 16. CONTROL register bit assignments

Bits Name Function

[31:4] - Reserved, res0

[3] SFPA

Indicates that the floating-point registers contain active state that belongs to the Secure state:

0 The floating-point registers do not contain state that belongs to the Secure state.

1 The floating-point registers contain state that belongs to the Secure state.

This bit is not banked between Security states and RAZ/WI from Non-secure state.

[2] FPCA

Indicates whether floating-point context is active:

0 No floating-point context active.

1 Floating-point context active.

This bit is used to determine whether to preserve floating-point state when processing an exception.

This bit is not banked between Security states.

[1] SPSEL

Defines the currently active stack pointer:

0 MSP is the current stack pointer.

1 PSP is the current stack pointer.

In Handler mode, this bit reads as zero and ignores writes. The Cortex

‑M33 core updates this bit

automatically on exception return.

This bit is banked between Security states.

[0] nPRIV

Defines the Thread mode privilege level:

0 Privileged.

1 Unprivileged.

This bit is banked between Security states.

Handler mode always uses the MSP, so the processor ignores explicit writes to the active stack pointer bit of the

CONTROL register when in Handler mode. The exception entry and return mechanisms automatically update the

CONTROL register based on the EXC_RETURN value.

In an OS environment, Arm

recommends that threads running in Thread mode use the process stack and the

kernel and exception handlers use the main stack.

By default, Thread mode uses the MSP. To switch the stack pointer that is used in Thread mode to the PSP,

either:

• Use the MSR instruction to set the CONTROL.SPSEL bit, the current active stack pointer bit, to 1.

• Perform an exception return to Thread mode with the appropriate EXC_RETURN value.

Note: When changing the stack pointer, software must use an ISB instruction immediately after the MSR instruction.

This ensures that instructions after the ISB instruction execute using the new stack pointer.

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2.1.4 Exceptions and interrupts

The Cortex

‑M33 processor implements all the logic required to handle and prioritize interrupts and other

exceptions. Software can control this prioritization using the NVIC registers. All exceptions are vectored and

except for reset, handled in Handler mode. Exceptions can target either Security state.

The NVIC registers control interrupt handling.

Related reference

Section 4.2 Nested Vectored Interrupt Controller

2.1.5 Data types and data memory accesses

The Cortex

‑M33 processor manages all data memory accesses as little-endian.

The processor supports the following data types:

• 32-bit words.

• 16-bit halfwords.

• 8-bit bytes.

• 32-bit single-precision floating-point numbers.

• 64-bit double-precision floating-point numbers.

2.1.6 The Cortex Microcontroller Software Interface Standard

The Cortex Microcontroller Software Interface Standard (CMSIS) simplifies software development by enabling the

reuse of template code and the combination of CMSIS-compliant software components from various middleware

vendors. Vendors can expand the CMSIS to include their peripheral definitions and access functions for those

peripherals.

For a Cortex

‑M33 microcontroller system, the CMSIS defines:

• A common way to:

– Access peripheral registers.

– Define exception vectors.

• The names of:

– The registers of the core peripherals.

– The core exception vectors.

• A device-independent interface for RTOS kernels, including a debug channel.

The CMSIS includes address definitions and data structures for the core peripherals in the Cortex

‑M33

processor.

This document includes the register names defined by the CMSIS, and short descriptions of the CMSIS functions

that address the processor core and the core peripherals.

Note: This document uses the register short names that are defined by the CMSIS. In a few cases these short names

differ from the architectural short names that might be used in other documents.

2.2

Cortex

M33 configurations

Table 17 shows the configuration for the STM32L5 and STM32U5 Series Cortex

M33.

Table 17. STM32L5xx and STM32U5xx Cortex

M33 configuration

Features STM32L5xx STM32U5xx

Security extension (TrustZone

)

Yes

(1)

DSP Yes

Floating Point Unit Yes, single precision floating point unit

MPU MPU secure (8 regions), MPU non-secure (8 regions)

SAU 8 regions

Interrupt priority levels 8 16

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2.3.2 Memory regions, types, and attributes

The memory map and the programming of the Secure and Non-secure MPUs splits memory into regions. If your

implementation has an MPU or has the Security Extension MPUs, programming the relevant MPUs splits memory

into regions.

The memory types are:

Normal The processor can reorder transactions for efficiency, or perform Speculative reads.

Device The processor preserves transaction order relative to other transactions to Device memory.

The additional memory attributes include:

Shareable For a shareable memory region, the memory system might provide data synchronization

between bus masters in a system with multiple bus masters, for example, a processor with

a DMA controller.

If multiple bus masters can access a Non-shareable memory region, software must ensure data

coherency between the bus masters.

Device memory is always Shareable.

<This description is required only if the device is likely to be used in systems where memory is

shared between multiple processors.>

Execute Never (XN) Means that the processor prevents instruction accesses. A MemManage fault exception is

generated on executing an instruction fetched from an XN region of memory.

2.3.3 Device memory

Device memory must be used for memory regions that cover peripheral control registers. Some of the

optimizations that are permitted for Normal memory, such as access merging or repeating, can be unsafe for

a peripheral register.

The Device memory type has several attributes:

G or nG Gathering or non-Gathering. Multiple accesses to a device can be merged into a single

transaction except for operations with memory ordering semantics, for example, memory barrier

instructions, load acquire/store release.

R or nR Reordering or non-Reordering.

E or nE Early Write Acknowledgement or no Early Write Acknowledgement.

For the Cortex‑M33 processor, only two combinations of these attributes are valid:

• Device-nGnRnE.

• Device-nGnRE.

Note: • Device-nGnRnE is equivalent to Armv7

‑

M Strongly Ordered memory type

• Device-nGnRE is equivalent to Armv7

‑

M Device memory.

• Device-nGRE and Device-GRE are new to the Armv8

‑

M architecture.

Typically, peripheral control registers must be either Device-nGnRE or Device-nGnRnE to prevent reordering of

the transactions in the programming sequences.

Note: Device memory is shareable, and must not be cached.

2.3.4 Secure memory system and memory partitioning

In an implementation with the Security Extension, the Security Attribution Unit (SAU) and Implementation Defined

Attribution Unit (IDAU) partition the 4GB memory space into Secure and Non-secure memory regions.

Note: The partitioning of the memory into Secure and Non-secure regions is independent of the Security state that the

processor executes in. See Section 2.5 Security state switches for more information on Security state.

Secure memory

partitioning

Secure addresses are used for memory and peripherals that are only accessible by Secure

software or Secure masters. Transactions are deemed to be secure if they are to an address

that is defined as Secure. Illegitimate accesses that are made by Non-secure software to

Secure memory are blocked and raise an exception.

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