VHDL设计：构建数字频率计

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity plcl is
port ( sysclk : in std_logic; --100MHZ频率输入
    inclk : in std_logic; --待测频率信号输入
    LCD1:out std_logic_vector(6 downto 0);  -----数码管显示档位，0为Hz,1为KHz，2为MHz
     LCD2:out std_logic_vector(6 downto 0);  -----数码管显示该档位下的个位
     LCD3:out std_logic_vector(6 downto 0);  -----数码管显示该档位下的十位
     LCD4:out std_logic_vector(6 downto 0));  -----数码管显示该档位下的百

end plcl;
architecture  behav of plcl is
signal cnt:std_logic_vector (29 downto 0);
signal clk_cnt:std_logic;
signal cntp1,cntp2,cntp3,cntp4,cntp5,cntp6,cntp7,cntp8:std_logic_vector (3 downto 0);
signal cntq1,cntq2,cntq3,cntq4,cntq5,cntq6,cntq7,cntq8:std_logic_vector (3 downto 0);
signal latch:std_logic_vector(3 downto 0);
signal A:std_logic_vector(3 downto 0):="0000";
signal B:std_logic_vector(3 downto 0):="0000";
signal C:std_logic_vector(3 downto 0):="0000";
signal D:std_logic_vector(3 downto 0):="0000";
begin
-------------0.5HZ分频--------------------------
process (sysclk)
begin
if sysclk'event and sysclk='1' then
if cnt=49999999 then 
clk_cnt <=not clk_cnt;
cnt <=(others=>'0');

else cnt<=cnt+1;
end if;
end if;
end process;
-------------计数----------------------------
process (inclk)
begin 
if inclk'event and inclk='1' then
if clk_cnt='1' then
 if cntp1="1001" then cntp1<="0000";
   if cntp2="1001" then cntp2<="0000";
     if cntp3="1001" then cntp3<="0000";
       if cntp4="1001" then cntp4<="0000";
          if cntp5="1001" then cntp5<="0000";
             if cntp6="1001" then cntp6<="0000";
                if cntp7="1001" then cntp7<="0000";
                     if cntp8="1001" then cntp8<="0000";
                     else cntp8<=cntp8+1; end if;
                  else cntp7<=cntp7+1; end if;
              else cntp6<=cntp6+1; end if;
            else cntp5<=cntp5+1; end if;
          else cntp4<=cntp4+1; end if;
       else cntp3<=cntp3+1; end if;
    else cntp2<=cntp2+1; end if;
  else cntp1<=cntp1+1; end if;
else
   if cntp1/="0000" or cntp2/="0000" or cntp3/="0000" or cntp4/="0000" or ---对计数值锁存
        cntp5/="0000" or cntp6/="0000" or cntp7/="0000" or cntp8/="0000" 
     then
         cntq1<=cntp1;cntq2<=cntp2;cntq3<=cntp3;cntq4<=cntp4;