A 20MHz 15µm Pitch 128x128 CTIA ROIC for InGaAs Focal Plane
Array
HUANG Zhangcheng*
,a,b
, CHEN Yu
a,b
, HUANG Songlei
a,b
, FANG Jiaxiong
a,b
a
State Key Laboratory of Transducer Technology, Shanghai Institute of Technical Physics, Chinese
Academy of Sciences, Shanghai 200083, P.R.China
b
Key Laboratory of Infrared Imaging Materials and Detectors, Shanghai Institute of Technical
Physics, Chinese Academy of Sciences, Shanghai 200083, P.R.China
ABSTRACT
A 128x128 matrix readout integrated circuit (ROIC) for 15x15 µm
2
InGaAs focal plane array (FPA) is reported in this
paper. Capacitive-feedback Trans-Impedance Amplifier (CTIA) and correlated double sampling (CDS) are both involved
in ROIC pixel which dissipates 90nW and has a full-well-capacity (FWC) of about 78,000 e-. Noises of ROIC pixel are
analyzed and distribution method of capacitors in pixel is discussed in order to obtain low-noise performance. In column
buffer circuit, a new pre-charging technique is developed to realize readout rate of 20 MHz with low power consumption.
The ROIC is fabricated with 0.18-µm 3.3 V mixed signal CMOS process. Test results show that the ROIC has an
equivalent input noise of about 181e- and can achieve a readout rate of 20 MHz.
Keywords: FPA, ROIC, small pixel pitch, high speed
1. INTRODUCTION
Driven by interest in higher resolution, pixel size reduction has been an objective for the research on infrared focal plane
arrays [1][2]. Over the past decade, pixel pitch of commercial detectors has been decreased from 50 µm to 15 µm and 12
µm [3]. New techniques such as 3D integration technology are developed to achieve pixel pitch of less than 10 µm [4].
As layout area of ROIC pixel decreases with the square of pixel pitch, one of the challenges for small-pixel ROIC design
is maintaining injection efficiency and low-noise performance. Benefit of advanced integrated circuit processes, enabling
same capability and functionality within small pixels can be achieved.
In this paper, a 128x128 matrix ROIC , namely M128U15, using 0.18-µm CMOS process for 15x15 µm
2
InGaAs focal
plane array (FPA) is reported. Architectures of input stage circuit and sample-hold (S/H) circuit in ROIC pixel are
presented in the second part. As shrinking the value of capacitors may lead to an increment in noise performance, noises
of ROIC pixel are analyzed and distribution method of capacitors is discussed in detail in the third section. Then, a new
pre-charging technique for column buffer is proposed to realize readout rate of 20 MHz with low power consumption.
Finally, test results of M128U15 are shown in the last section.
Proc. of SPIE Vol. 9275, 92750T · © 2014 SPIE · CCC code: 0277-786X/14/$18 · doi: 10.1117/12.2074196
Proc. of SPIE Vol. 9275 92750T-1