TI CDCI6214: 低功耗时钟发生器技术文档

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Signal

Generator

Sine

Wave

Modulator

Reference

Input

Device Output

Power Supply

Balun

Phase Noise/

Spectrum

Analyzer

DUT

STOP

START

STOP

BUS

SU_STA

SDA

SCL

H_STA

SU_SDA

PWL_SCL

PWH_SCL

H_SDA

SU_STOP

ACK

DUT

HCSL

50 

33 

Differential impedance 100 

>100 k

< 1 pF

GND

< 1 pF

GND

High

Impedance

Probe

1 pF

TI: 3.5 in

33 

CDCI6214

ZHCSGV7E –JULY 2017–REVISED JANUARY 2020

www.ti.com.cn

Parameters (continued)

(1) Measured using Tektronix DPO75902SX oscilloscope. Recommended to use an oscilloscope bandwidth setting of 4/8

GHz and vertical setting of 50mV/division. Data processed using Clock Jitter Tool: Ver:1.6.7.2.

Figure 14. HCSL PCIe Test Load Setup

7.1.3 Serial Interface

Figure 15. I

C Timing

7.1.4 Power Supply

Figure 16. PSNR Setup

chX

PLL

chX_iod_mux

ip_byp_en_chX

ch0_lvcmos_drv

XOUT/FB_P

REFSEL

XIN/FB_N

REFP

REFN

OSC

ip_byp_mux

xin_inbuf_ctrl

ip_xo_gm

ip_xo_gm_fine

ip_xo_cload

Internal

Zero Delay

Feedback

ip_rdiv

ip_rdiv = 0

ip_rdiv t 1

ref_inbuf_ctrl

ref_mux

ref_mux_src

PLL

ip_byp_en_y0

CDCI6214

ZHCSGV7E –JULY 2017–REVISED JANUARY 2020

www.ti.com.cn

8.3 Feature Description

The following sections describe the individual blocks of the CDCI6214 ultra-low power clock generator.

8.3.1 Reference Block

A reference clock to the PLL is fed to pins 1 (XOUT/FB_P) and 2 (XIN/FB_N) or to pins 5 (REFP) and 6 (REFN).

There are multiple input stages available to adapt to many clock references. The bit-fields that control the

reference input type selection are xin_inbuf_ctrl and ref_inbuf_ctrl.

The reference mux selects the reference for the PLL and the PLL-bypass path. For debug purposes ip_byp_mux

allows to connect the reference divider or doubler output to the clock distribution.

The buffers for the PLL-bypass path can be individually enabled and disabled using ip_byp_en_ch[4:1] and

ip_byp_en_y0.

Figure 18. Reference Block

8.3.1.1 Input Stages

8.3.1.1.1 Crystal Oscillator

The XIN and XOUT pins provide a crystal oscillator stage to drive a fundamental mode crystal in the range of 8

MHz to 50 MHz. The crystal input stage integrates a tunable load capacitor array up to 9 pF using ip_xo_cload.

The drive capability of the oscillator is adjusted using ip_xo_gm.

8.3.1.1.2 LVCMOS

The LVCMOS input buffer threshold voltage follows VDDREF. This helps to use the device as a level shifter as

the outputs have separate supplies.

8.3.1.1.3 Differential AC-Coupled

The differential input stage has an internal bias generator and should only be used with AC-coupled reference

inputs.

8.3.1.2 Reference Mux

Either XIN or REF can be selected as reference to the PLL and clock distribution path. The reference mux is

controlled using the REFSEL pin with ref_mux_src = 0 or the ref_mux bit-field with ref_mux_src = 1.

8.3.1.3 Reference Divider

A reference divider can be used to divide higher input frequencies to the permitted PFD range. It supports

division values of 1 to 255 using ip_rdiv.

CDCI6214

www.ti.com.cn

ZHCSGV7E –JULY 2017–REVISED JANUARY 2020

Feature Description (continued)

(1) 'x' allows any possible bit-field value. An entry of 'A', 'B' or 'C' indicates the same bit-field value.

(2) For internal feedback channel 2 is required. For external feedback the output clock connected to FB_P/N is recommended to have same

settings as default PLL feedback path.

8.3.1.3.1 Doubler

The reference path contains a doubler circuit. It is used to double the input frequency and can be used to

achieve the highest PFD update frequency of 100 MHz using a 50-MHz crystal. The doubler activates using

ip_rdiv = 0.

8.3.1.4 Bypass-Mux

The input reference or the input to the PFD can be routed to the bypass path using ip_byp_mux.

8.3.1.5 Zero Delay, Internal and External Path

In zero delay mode the REF input clock is used as reference clock at the PFD. The FB_P clock (LVCMOS) or

FB_P/N clock (differential) can be used to feed an external source as feedback clock to the PFD. The external

feedback path is recommended for zero delay operation. Moreover there is an additional internal feedback path

which is sourced by output channel 2.

Table 1. Zero Delay Operation

(1)

Operation Reference Feedback

REFSEL ref_mux

ref_mux_

src

ip_rdiv

ref_inbuf

_ctrl

xin_inbuf

_ctrl

zdm_mo

zdm_cloc

ksel

zdm_aut

pll_psfb pll_psa pll_ndiv

ch2_iod_

div

(2)

Normal PLL, XIN

Reference

L x 0 1 x 0 0 x x x x x x

Normal PLL, REF

Reference

H x 0 1 x x 0 x x x x x x

Normal PLL, REF

Reference

x 1 1 1 x x 0 x x x x x x

Zero Delay, Internal

Feedback

x 1 1 1 A A 1 0 1 B B C C

Zero Delay, External

Feedback

x 1 1 1 A A 1 1 1 B B C C

8.3.2 Phase-Locked Loop

The CDCI6214 contains a fully integrated phase-locked loop circuit. The error between a reference phase and an

internal feedback phase is compared at the phase-frequency-detector. The comparison result is fed to a charge

pump that is connected to an integrated loop filter. The control voltage resulting from the loop filter tunes an

internal voltage-controlled oscillator (VCO). The frequency of the VCO is fed through a pre-scaler feedback

divider (PSFB) and another feedback divider back to the PFD.

The PLL closed-loop bandwidth is configurable using registers PLL0, PLL1, and PLL2.

• Integer PLL

• PFD operates 1 MHz to 100 MHz

• Live Lock-Detector provides PLL lock status on status pin and bit lock_det (there is an additional sticky bit

unlock_s)

• Integrated selectable loop filter components

• For 25-MHz PFD bandwidths between 100 kHz and 3000 kHz can be achieved to optimize PLL to input

reference

• Voltage-Controlled Oscillator (VCO) tuning range of 2400 to 2800 MHz

• VCO is compatible to 0.5% spread spectrum (SSC) references at 100 MHz.

pll_lf_zcap

pll_lf_res

Phase

Frequency

Detector

Res

Zcap

Pcap

Charge

Pump

14 Bit

Feedback Divider

/4, /5 /6

Feedback Pre-Scaler

Reference Clock

Feedback Clock

Voltage Controlled

Oscillator

Clock Distribution

/4, /5 /6

Clock Distribution

Pre-Scaler B

/4, /5 /6

Clock Distribution

Pre-Scaler A

Divider

Synchronization

GND

pll_lf_pcap

pll_psfbpll_ndiv

pll_psa

pll_psb

pll_cp_dn

pll_cp_up

FB_P/N

Internal (CH2)

zdm_mode

zdm_clocksel

CDCI6214

ZHCSGV7E –JULY 2017–REVISED JANUARY 2020

www.ti.com.cn

(1) All values typical design targets.

(2) Program same value to pll_cp_dn.

Figure 19. Phase-Locked Loop Circuit

Table 2. Common Clock Generator Loop Filter Settings

(1)

VCO

in MHz f

PFD

in MHz BW in MHz

Phase

Margin in °

Damping

Factor

in mA C

Pcap

IN pF R

Res

IN kΩ C

Zcap

IN pF

pll_cp_up

(2)

pll_lf_pcap pll_lf_res pll_lf_zcap

2400 25 0.51 67 0.9 2.0 17.5 2.5 450

2400 50 0.97 67 1.3 2.0 17.5 2.5 450

2400 100 1.41 68 1.2 2.4 17.5 1.5 450

2457.6 61.44 1.04 67 1.4 1.8 17.5 2.5 450

2500 25 0.49 67 0.9 2.0 17.5 2.5 450

2500 50 0.93 68 1.3 2.0 17.5 2.5 450

2680 67 0.38 67 1.3 0.2 19.5 5.5 480

2688 48 0.93 68 1.3 1.5 17.5 2.5 480

2688 96 0.36 67 1.0 0.2 19.5 3.5 480

2800 50 1.00 68 1.0 2.6 17.5 1.5 450

2800 100 1.00 68 1.0 1.3 17.5 1.5 450

8.3.3 Clock Distribution

The VCO connects to two individually configurable pre-scaler dividers sourcing the on-chip clock distribution.

The clock distribution consists of four output channels. Each output channel contains a divider with integer

division and synchronization capabilities.

A mux after each divider allows to feed the generated frequency to the adjacent output buffers. Thus for single

frequency clock generation only a single output divider needs to be active.

The output buffers are compatible to various signaling standards: LVDS, CML-like, LVPECL-like, LVCMOS and

HCSL using ch1_outbuf_ctrl.

• HCSL must be directly connected to a load termination to ground. A series resistance can be used to adapt to

the trace impedance.

• LVDS requires a differential termination connected between the positive and negative output buffer pins. The

termination can be connected directly or using AC-coupling. When using the LVDS output type, set

ch1_1p8vdet, ch2_1p8vdet, ch3_1p8vdet, andch4_1p8vdet to match the VDDO12 and VDDO34.

• CML and LVPECL are only supported in an AC-coupled configuration. The receiver and the termination may

only be connected through AC-coupling capacitors to the device pins.

• LVCMOS outputs are designed for capacitive loads only. A series resistance should be used to adapt the

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