Altera FPGA视频与图像处理示例设计解析

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"该资源是Altera公司发布的关于FPGA应用的一个实例，专注于视频和图像处理，适用于Cyclone III系列。文档日期为2011年6月，设计示例展示了如何动态缩放和裁剪标准定义的NTSC或PAL格式的视频流，并实现画中画功能，将视频流以高清1024×768分辨率通过数字视频接口（DVI）输出。设计中使用了Video and Image Processing Suite中的可参数化MegaCore函数，这些函数可用于快速开发视频和图像处理系统，并能与视频接口、处理器和外部内存控制器完全集成。" 详细说明: Altera的FPGA资料实例主要关注的是视频和图像处理技术在Cyclone III FPGA系列中的应用。这个示例设计涵盖了多种关键功能，包括： 1. 动态缩放：设计能够对输入的NTSC或PAL格式的视频流进行实时的缩放处理，适应不同的显示需求。 2. 裁剪：除了缩放，设计还支持对视频流的裁剪，可以按需选择视频画面的特定部分进行显示。 3. 画中画（Picture-in-Picture）混合：此设计还实现了画中画功能，允许在一个主视频流中嵌入一个背景层，这在电视广播、监控系统等场景中非常实用。 4. 高清输出：经过处理的视频流通过DVI接口以1024×768的高清分辨率输出，满足高清晰度显示的需求。 5. 使用Video and Image Processing Suite：设计利用了Altera的Video and Image Processing Suite提供的MegaCore函数库，这是一个强大的工具集，包含了一系列可配置的IP核，用于构建视频和图像处理系统。 6. 集成性：这些MegaCore函数能够与各种视频接口、处理器以及外部内存控制器无缝对接，简化系统集成，加速开发进程。 7. 开发板平台：示例设计是在Altera Cyclone III EP3C120开发板上实现的，该开发板提供了硬件平台来验证和测试设计的功能。为了深入了解这些MegaCore函数及其具体用法，用户可以参考Video and Image Processing Suite User Guide，该指南提供了详细的函数描述和技术指导。总结来说，这个FPGA资料实例是一个强大的学习资源，对于想要在FPGA上实现高效视频和图像处理解决方案的工程师来说，具有很高的参考价值。它不仅展示了实际操作中的应用案例，还提供了快速开发所需的技术基础，有助于缩短产品开发周期并优化系统性能。

Page 10 Functional Description

Video and Image Processing Example Design © June 2011 Altera Corporation

All Video and Image Processing Suite MegaCore functions (except the Line Buffer

Compiler) transmit data using the Avalon-ST Video protocol, which increases

productivity through design flexibility and reuse.

f For details about the Avalon-ST Video protocol, refer to the to the Interfaces chapter in

the Video and Image Processing Suite User Guide.

The Clocked Video Input function strips the incoming clocked video of horizontal and

vertical blanking, leaving active picture data. Using this data with horizontal and

vertical synchronization information, the Clocked Video Input function creates the

necessary Avalon-ST Video control and active picture packets.

The active picture data is not converted; the color plane information remains the same

as in the clocked video format.

The clocked video input also provides clock crossing capabilities to allow video

formats running at different frequencies to enter the system. The clocked video input

also provides greater design flexibility by enabling the video processing system clock

to be decoupled from the video input pixel clock. In this example, the pixel clock is

27MHz and the system clock is 100MHz.

In addition to configuring the TVP5154 decoder chip, the Nios II processor starts the

clocked video input.

Video Processing

The NTSC video stream input into the processing data path is 8 bits wide, in YCbCr

4:2:2 interlaced format, with each field input containing 720 pixels per line, and either

244 lines for each even field (f0) and 243 lines for each odd field (f1). The Luma (Y)

and the Chroma (Cb and Cr) color planes are transmitted in sequence in the CbYCrY

order.

The first processing function in the data path clips a rectangular region of 720 pixels

by 240 lines from each field, offset three lines from the top of the field, and outputs

fields with an equal number of odd and even lines, for further processing.

The clipped image video data is then converted from two colors in sequence (the

Luma (Y) and Chroma (C) color planes) to two colors in parallel, using the Color

Plane Sequencer MegaCore function. This operation demonstrates how you can

change the format of the video data to suit the processing requirements of the

functions in the data path and to satisfy the performance requirements of the

application.

The Avalon-ST video data is chroma resampled to YCbCr 4:4:4 format prior to

converting the color space to RGB from YCbCr. The interlaced video is then

deinterlaced using a motion adaptive algorithm to produce a video stream in

progressive format.

1 The chroma resampling is applied before the motion adaptive deinterlacing because

the motion adaptive algorithm requires the input color channels to have the same

sampling rate.

Review the Example Design Page 11

To allow run-time clipping every frame, a second clipper function is connected to the

output from the deinterlacer. When the field resolution input to the motion adaptive

deinterlacer changes, up to four fields might be required before the deinterlacer

produces valid data. This delay is caused by the motion adaptive algorithm buffering

two previous frames of the new video resolution to calculate the output pixel values.

The clipped progressive video stream is then scaled using the polyphase algorithm of

the parameterizable scaling function (with four horizontal and four vertical taps).

To smooth out the burstiness of the video data flow, the frame buffer buffers the

scaled video stream in external memory. The frame buffer also manages the rate

change across the system video input and output by dropping and repeating video

frames.

The video data output from the mixer is streamed into the clocked video output

function, which supplies the DVI interface.

A DDR2 High Performance Memory Controller II buffers the video frames from both

the frame buffer and the deinterlacing function in the video data path.

Video Output

A video stream (progressive RGB data) is output via the DVI Tx port on the Bitec

HSMC DVI input/output daughtercard. The Nios II processor controls the

configuration of the TFP410 DVI chip by writing or reading data to or from the I2C

bus master component, which performs writes and reads on the external bus as

requested.

The Clocked Video Output MegaCore function converts from the Avalon-ST Video

protocol to clocked video formats (such as BT656 and DVI). The Clocked Video

Output MegaCore function formats Avalon-ST Video into clocked video by inserting

horizontal and vertical blanking and generating horizontal and vertical sync

information using the Avalon-ST Video control and active picture packets. The active

picture data is not converted; the color plane information remains the same as in the

Avalon-ST Video format.

The clocked video output also provides clock crossing capabilities to provide greater

design flexibility by enabling the video processing system clock to be decoupled from

the video output pixel clock. In this example the output pixel clock is 65MHz and the

system clock is 100MHz.

In addition, the clocked video output provides a queue where pixels can wait when

the DVI output is in blanking and does not require pixel data. If this FIFO becomes

full, then the flow controlled interface indicates that the clocked video output is not

ready for data and earlier parts of the pipe are stalled.

Review the Example Design

This section describes how to construct a video processing application using the

Altera video and image processing framework as demonstrated through the Video

and Image Processing example design. This section includes a description of the

top-level design file in the Quartus II software, the full hardware system in Qsys, and

the configuration and control software code in the Nios II SBT for Eclipse.

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