"JEDEC发布GDDR4标准规范，提供高性能图形双倍数据传输技术"

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JEDEC SDRAM 3_11_5_8_R16.01-2023 Graphics Double Data (GDDR4) is a standardized specification for Graphics Double Data Rate (GDDR4) Synchronous Graphics Random Access Memory (SGRAM). This specification is outlined in the document "JEDEC SDRAM 3_11_5_8_R16.01-2023 Graphics Double Data (GDDR4) SGRAM Standard.pdf" and falls under JEDEC Standard No. 21-C-i-3.11.5.8. The scope of the GDDR4 SGRAM specification is outlined as being comprehensive and detailed, covering all aspects of the design, features, and functionality of GDDR4 memory modules. The features of GDDR4 SGRAM are highlighted as being advanced and tailored specifically for graphics processing units (GPUs). These features include high-speed data transfer rates, low power consumption, and optimized for high-resolution graphics rendering. The functional design of GDDR4 SGRAM is detailed in the specification, outlining the architecture, data pathways, and control mechanisms of the memory module. The document provides in-depth technical information about the inner workings of GDDR4 SGRAM and how it interfaces with GPU devices. Overall, the GDDR4 SGRAM specification is a comprehensive and detailed document that provides a standardized framework for the design, features, and functionality of graphics memory modules. This ensures interoperability between different hardware components and enables seamless integration of GDDR4 SGRAM into various graphics processing systems.

JEDEC Standard No. 21-C

Page 3.11.5.8 – 10

Release 16.01

4.2.2 DQ Termination

DQ Termination is used in combination with Driver Strengths/Termination setting to define the value for

the on-die termination for the DQ, DM, and WDQS pins.

GDDR4 SGRAM’s DQ Termination supports values of 1/4 ZQ or 1/2 ZQ intended for a single- or dual-

loaded system. DQ Termination is set with bits A2 and A3 during an MRS command to EMR. The ZQ

value is controlled by the EMR Driver Strengths/Termination setting.

The DQ Termination setting is also used to turn off the on-die termination on a GDDR4 SGRAM. If A3

and A2 are set 00, all DQ, DM, WDQS and Command/Address terminators on the device are disabled. If

A3 and A2 are set 01 all DQ, DM, WDQS Terminations are switched off but Command/Address

terminators are still enabled. GDDR4 adds a mode where only the DQS termination is on (see EMR3

LPTERM). The LPTERM mode is only valid if A3 and A2 are set to either 10 or 11.

To assure that address/command termination is enabled during initialization, the GDDR4 SGRAM

automatically sets EMR bits A3 and A2 and EMR3 bit A5 to a default setting during the 200 us window

after power/clock stabilization. The default setting for EMR[A3:A2] is either 01, 10 or 11, and for

EMR3[A5] is 0.

4.2.3 Preamble

The READ and WRITE preamble in GDDR4 SGRAMs is programmable using bits A4 - A6. Values of 1-5

are specified. Additional cycles of preamble may be required to attain the desired frequency. It is

recommended that Controller manufacturers support all values. Manufacturer datasheets should be

consulted as the maximum number of preamble cycles over clock frequency which is supported by the

GDDR4 SGRAM for Read commands is vendor specific and will be defined by each vendor’s

specification.

4.2.4 DLL Enable/Disable

The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and

upon returning to normal operation after disabling the DLL for debugging or evaluation as well as low

power operation. (When the device exits self refresh mode in normal operation, the DLL is enabled

automatically.) Any time the DLL is enabled, t

must be met before a READ command can be issued.

4.2.5 DBI

Data Bus Inversion (DBI) for READ and WRITE is selected independently using bit A8 for read and bit A9

for write. The mode of DBI is selected using bit A10. For more details on DBI see DBI in the Operation

clause.

4.2.6 Vendor ID

Vendor ID is used to identify the manufacture of the GDDR4 SGRAM. For more details on Vendor ID see

clause entitled VENDOR ID, PARITY, and SCAN for more details.

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JEDEC

JEDEC Standard No. 21-C

Page 3.11.5.8 – 11

Release 16.01

4.3 EXTENDED MODE REGISTER 2 (EMR2)

The Extended Mode Register 2 controls functions beyond those controlled by the Mode Register and

Extended Mode Register; these additional functions include the offset for both the driver and termination

and t

RAS

as shown in Figure 5.

The Extended Mode Register 2 is programmed via the MODE REGISTER SET (MRS) command (with

BA0=0, BA0=1 and BA2=0) and will retain the stored information until it is reprogrammed or the device

loses power. The Extended Mode Register 2 must be loaded when all banks are idle and no bursts are in

progress, and the controller must wait the specified time t

MRD

before initiating any subsequent operation.

Violating either of these requirements will result in unspecified operation.

Reserved states should not be used, as unknown operation or incompatibility with future versions may

result. RFU bits are reserved for future use and must be programmed to 0.

Figure 5 — Extended Mode Register 2 Definition

4.3.1 RAS

RAS must be programmed into bits A6-A11 with a value greater than or equal to RU{tRAS/tCK}, where

RU stands for round up, tRAS is the analog value from the vendor datasheet and tCK is the operating

clock cycle time.

If the DRAM vendor does not support the Mode Register definition of tRAS in clock cycles, the Mode

vendor datasheet. If the DRAM vendor supports the clock cycle definition of tRAS, it is mandatory to

support all optional clock cycles.

OCD-Termination

/PullUp- offset

BA1 BA0 A9 A8

A7 A6 A5 A4 A3 A2 A1 A0

A11 A10BA2

A12

0 1 3

-21

-41

-31

1 1 -1

RASRFU

RASA9 A8 A7

2/optional0 0

RFU0 0

1/optional0 0

0 0 1 3/optional

6/optional0 1

4/optional0 1

5/optional0 1

0 1 1 7/optional

10/optional1 0

8/optional1 0

9/optional1 0

1 0 1 11/optional

12/optional1 1

A10

14/optional1 1

13/optional1 1

1 1 1 15/optional

OCD-PullDown-Driver

offset

OCD Termination/

PullUp offset

0 1 3

-21

-41

-31

1 1 -1

OCD

PullDown

Driver offset

A1 A0

1 0 0 24/optional01

1 0 0 25/optional11

1 0 1 26/optional01

1 1 1 63/optional11

A11

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JEDEC

JEDEC Standard No. 21-C

Page 3.11.5.8 – 12

Release 16.01

4.3.2 OCD PullDown Driver and Termination PullUp Driver Offset

GDDR4 SGRAM adds the ability to add or subtract offsets from both the Driver and Terminator. See

clause entitled DRIVER and TERMINATION for more details.

4.4 EXTENDED MODE REGISTER 3 (EMR)

The Extended Mode Register 3 controls functions beyond those controlled by the Mode Register,

Extended Mode Register and Extended Mode Register 2; these additional functions include LPTERM

and Parity as shown in Figure 6.

The Extended Mode Register 3 is programmed via the MODE REGISTER SET (MRS) command (with

BA0=1, BA1=1 and BA2=0) and will retain the stored information until it is reprogrammed or the device

loses power. The Extended Mode Register 3 must be loaded when all banks are idle and no bursts are in

progress, and the controller must wait the specified time t

MRD

before initiating any subsequent operation.

Violating either of these requirements will result in unspecified operation.

If the user activates bits in the Extended Mode Register 3 in an optional field, either the optional field is

activated (if option is implemented in the device) or no action is taken by the device (if option is not

implemented). Reserved states should not be used, as unknown operation or incompatibility with future

versions may result. RFU bits are reserved for future use and must be programmed to 0.

Figure 6 — Extended Mode Register 3 Definition

4.4.1 LPTERM

GDDR4 SGRAM adds a low power mode which reduces power consumed for I/O termination by

disabling the termination for a subset of the pins. See clause entitled DRIVER and TERMINATION for

more details.

4.4.2 DRAM Info

DRAM info is used to select either Parity info or Vendor ID info to be output.

RFU1 1

BA1 BA0 A9 A8

A7 A6 A5 A4 A3 A2 A1 A0

A11 A10BA2

A12

Parity Mask

Parity

Reset

Parity

Enable

Parity Mask

(optional)

A10A11

DQ[7:0]0

DQ[15:7]1

DQ[23:16]0

DQ[31:24]1

Parity Reset

(optional)

Reset

Store

Parity Enable

(optional)

Enable

Disable

DRAM InfoRFU

DRAM Info

A6A7

Vendor ID0

Vendor Specific0

Vendor Specific11

PERR_Info/optional

TERM

LPTERM

Enabled

Disabled

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JEDEC

JEDEC Standard No. 21-C

Page 3.11.5.8 – 13

Release 16.01

4.4.3 Parity

Parity is an optional feature of GDDR4 SGRAMs. Parity is enabled using bit A9. Parity is stored and reset

using bit A8. A mask which selects which bits to monitor can be used by selecting bits A10 - A11. Parity

Mask, Parity Enable and Parity Reset are optional features. If the Parity feature is implemented all Parity

Mode Register Bits must be supported. See the clause entitled VENDOR ID, PARITY, and SCAN for

more details.

5 COMMAND and ADDRESS

5.1 Addressing

GDDR4 SGRAMs use a multiplexed address scheme to reduce pins required on the GDDR4 SGRAM as

shown in Table 3. The addresses should be provided to the GDDR4 SGRAM in two parts that are latched

into the memory with two consecutive clock edges. Command protocols incorporating signals such as

CS#, RAS#, CAS# and WE# should be issued at the first rising edge of the clock and half of the

addresses will be registered along with command inputs. Following this cycle, the remaining half of the

addresses will be registered at the next rising edge of the clock.

The commands such as ACTIVE, READ, READ with autoprecharge, WRITE, WRITE with

autoprecharge, Precharge, Precharge all, MODE REGISTER SET, Auto-refresh and Self-refresh require

two consecutive clocks to fulfill a single task. Only NOP command can be registered at single clock

cycle. The clock reference for the AC timing is defined as the first rising edge of the clock.

It is prohibited to issue any other command at the second clock cycle which has been reserved for the

second half of the addresses for the preceding command.

GDDR4 addressing includes support for 8Mx32, 16Mx32 and 32Mx32 GDDR4 SGRAM. For both the

32Mx32 and the 16Mx32, two addressing options are allowed (2 KB or 4 KB page size). 8Mx32 GDDR4

SGRAMs are quad-bank and 16Mx32 and 32Mx32 GDDR4 SGRAMs are eight-bank devices.

Table 3 — Address Pairs

Clock

First BA2 BA1 BA0 A12 A11 A10 A9 A8

Second A6 A5 A1 A2 A3 A0 A7 A4

Table 4 — Addressing Scheme

8Mx32 16Mx32 32Mx32

Row address A0~A11 A0~A10 A0~A11 A0~A11 A0~A12

Column address A0~A7,A9 A0~A7,A9,A10 A0~A7,A9 A0~A7,A9,A10 A0~A7,A9

Bank address BA0~BA1 BA0~BA2 BA0~BA2 BA0~BA2 BA0~BA2

Autoprecharge A8 A8 A8 A8 A8

Refresh 4K/32 ms 4K/32 ms 8K/32 ms 8K/32 ms 16K/32 ms

Refresh period 7.8 µs 7.8 µs 3.9 µs 3.9 µs 1.9 µs

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JEDEC

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