STM32G071x8xB Cortex-M0+ MCU数据手册：高性能低功耗特性

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"STM32G071x8xB 数据手册.pdf 提供了关于STM32G071x8xB系列微控制器的详细规格和技术特性，这是一款基于Arm Cortex-M0+内核的32位MCU，适用于广泛的嵌入式应用。" STM32G071x8/B系列是意法半导体（STMicroelectronics）推出的高性能、低功耗的微控制器，主要特点包括： 1. **核心处理器**：搭载了Arm Cortex-M0+内核，工作频率最高可达64MHz，为系统提供高效能处理能力。 2. **温度范围**：工作温度范围广泛，可在-40°C至85°C，甚至在扩展温度范围内可达125°C，适应各种环境条件。 3. **内存配置**：包含高达128KB的闪存（Flash memory），用于存储程序代码；36KB的SRAM，其中32KB带有硬件奇偶校验检查，保证数据安全。 4. **错误检测与校验**：集成了CRC计算单元，用于数据完整性检查。 5. **电源管理**：支持1.7V到3.6V的电压范围，具备POR（上电复位）、PDR（掉电复位）、BOR（可编程brown-out复位）以及PVD（可编程电压检测器）。同时提供了多种低功耗模式，如睡眠、停止、待机和关闭，以及VBAT供电，用于RTC（实时时钟）和备份寄存器。 6. **时钟系统**：具备4到48MHz的晶体振荡器，32kHz晶体振荡器带校准功能，16MHz的内部RC振荡器可选配PLL（锁相环），以及一个±5%精度的32kHz内部RC振荡器。 7. **输入/输出接口**：最多60个快速I/O，所有I/O口都可以映射到外部中断向量，部分I/O具有5V耐压能力，增强了对外部设备的支持。 8. **DMA控制器**：7通道DMA控制器，提供灵活的映射，提高数据传输效率。 9. **模拟功能**：集成12位ADC（模数转换器），转换速度达0.4µs，支持最多16个外部通道，可通过硬件过采样提升至16位精度。 10. **其他外设**：还包含了定时器、DAC（数模转换器）、通信接口等，这些丰富的外设选项使得STM32G071x8/B系列微控制器适合于多种应用场景，如工业控制、物联网设备、智能家居、消费电子等。该数据手册详细介绍了STM32G071x8/B系列的电气特性、引脚描述、功能配置、接口操作、电源管理策略、时钟系统设置、调试工具支持、软件开发工具和生态系统等，是开发基于STM32G071x8/B的嵌入式系统的必备参考资料。

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Functional overview STM32G071x8/xB

16/136 DS12232 Rev 2

3.5 Boot modes

At startup, the boot pin and boot selector option bit are used to select one of the three boot

options:

• boot from User Flash memory

• boot from System memory

• boot from embedded SRAM

The boot pin is shared with a standard GPIO and can be disabled through the boot selector

option bit. The boot loader is located in System memory. It manages the Flash memory

reprogramming through USART on pins PA9/PA10, PC10/PC11 or PA2/PA3, through I

C-

bus on pins PB6/PB7 or PB10/PB11, or through SPI on pins PA4/PA5/PA6/PA7 or

PB12/PB13/PB14/PB15.

3.6 Cyclic redundancy check calculation unit (CRC)

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a

configurable generator polynomial value and size.

Among other applications, CRC-based techniques are used to verify data transmission or

storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of

verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of

the software during runtime, to be compared with a reference signature generated at link

time and stored at a given memory location.

3.7 Power supply management

3.7.1 Power supply schemes

The STM32G071x8/xB devices require a 1.7 V to 3.6 V operating supply voltage (V

Several different power supplies are provided to specific peripherals:

• V

= 1.7 (2.0) to 3.6 V

is the external power supply for the internal regulator and the system analog such

as reset, power management and internal clocks. It is provided externally through

VDD/VDDA pin.

The minimum voltage of 1.7 V corresponds to power-on reset release threshold

POR(MAX)

. Once this threshold is crossed and power-on reset is released, the

functionality is guaranteed down to power-down reset threshold V

PDR(MIN)

• V

DDA

= 2.0 V (ADC and COMP) / 1.8 V (DAC) / 2.4 V (VREFBUF) to 3.6 V

DDA

is the analog power supply for the A/D converter, D/A converter, voltage

reference buffer and comparators. V

DDA

voltage level is identical to V

voltage as it is

provided externally through VDD/VDDA pin.

• V

DDIO1

= V

DDIO1

is the power supply for the I/Os. V

DDIO1

voltage level is identical to V

voltage

as it is provided externally through VDD/VDDA pin.

• V

BAT

= 1.55 V to 3.6 V

BAT

is the power supply (through a power switch) for RTC, TAMP, low-speed external

32.768 kHz oscillator and backup registers when V

is not present. V

BAT

is provided

DS12232 Rev 2 17/136

STM32G071x8/xB Functional overview

externally through VBAT pin. When this pin is not available on the package, VBAT

bonding pad is internally bonded to the VDD/VDDA pin.

• V

REF+

is the input reference voltage for the ADC and DAC, or the output of the internal

voltage reference buffer (when enabled). When V

DDA

< 2 V, V

REF+

must be equal to

DDA

. When V

DDA

≥ 2 V, V

REF+

must be between 2 V and V

DDA

. It can be grounded

when the ADC and DAC are not active.

The internal voltage reference buffer supports two output voltages, which is configured

with VRS bit of the VREFBUF_CSR register:

–V

REF+

around 2.048 V (requiring V

DDA

equal to or higher than 2.4 V)

–V

REF+

around 2.5 V (requiring V

DDA

equal to or higher than 2.8 V)

REF+

is delivered through VREF+ pin. On packages without VREF+ pin, V

REF+

internally connected with V

, and the internal voltage reference buffer must be kept

disabled (refer to datasheets for package pinout description).

• V

CORE

An embedded linear voltage regulator is used to supply the V

CORE

internal digital

power. V

CORE

is the power supply for digital peripherals, SRAM and Flash memory.

The Flash memory is also supplied with V

Figure 2. Power supply overview

3.7.2 Power supply supervisor

The device has an integrated power-on/power-down (POR/PDR) reset active in all power

modes except Shutdown and ensuring proper operation upon power-on and power-down. It

maintains the device in reset when the supply voltage is below V

POR/PDR

threshold, without

the need for an external reset circuit. Brownout reset (BOR) function allows extra flexibility. It

MSv39736V2

DDA

domain

RTC domain

D/A converter

A/D converter

Standby circuitry

(Wakeup, IWDG)

Voltage

regulator

Core

SRAM

Digital

peripherals

Low-voltage

detector

LSE crystal 32.768 kHz osc

BKP registers

RCC BDCR register

RTC and TAMP

2 x comparator

Voltage reference buffer

I/O ring

CORE

domain

Temp. sensor

Reset block

PLL, HSI

Flash memory

DDIO1

VREF+

domain

CORE

VSS/VSSA

VDD/VDDA

VBAT

DDA

REF+

SSA

DDIO1

domain

Functional overview STM32G071x8/xB

18/136 DS12232 Rev 2

can be enabled and configured through option bytes, by selecting one of four thresholds for

rising V

and other four for falling V

The device also features an embedded programmable voltage detector (PVD) that monitors

the V

power supply and compares it to V

PVD

threshold. It allows generating an interrupt

when V

level crosses the V

PVD

threshold, selectively while falling, while rising, or while

falling and rising. The interrupt service routine can then generate a warning message and/or

put the MCU into a safe state. The PVD is enabled by software.

3.7.3 Voltage regulator

Two embedded linear voltage regulators, main regulator (MR) and low-power regulator

(LPR), supply most of digital circuitry in the device.

The MR is used in Run and Sleep modes. The LPR is used in Low-power run, Low-power

sleep and Stop modes.

In Standby and Shutdown modes, both regulators are powered down and their outputs set in

high-impedance state, such as to bring their current consumption close to zero. However,

SRAM data retention is possible in Standby mode, in which case the LPR remains active

and it only supplies the SRAM.

3.7.4 Low-power modes

By default, the microcontroller is in Run mode after system or power reset. It is up to the

user to select one of the low-power modes described below:

• Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can

wake up the CPU when an interrupt/event occurs.

• Low-power run mode

This mode is achieved with V

CORE

supplied by the low-power regulator to minimize the

regulator's operating current. The code can be executed from SRAM or from Flash,

and the CPU frequency is limited to 2 MHz. The peripherals with independent clock can

be clocked by HSI16.

• Low-power sleep mode

This mode is entered from the low-power run mode. Only the CPU clock is stopped.

When wakeup is triggered by an event or an interrupt, the system reverts to the Low-

power run mode.

• Stop 0 and Stop 1 modes

In Stop 0 and Stop 1 modes, the device achieves the lowest power consumption while

retaining the SRAM and register contents. All clocks in the V

CORE

domain are stopped.

The PLL, as well as the HSI16 RC oscillator and the HSE crystal oscillator are

disabled. The LSE or LSI keep running. The RTC can remain active (Stop mode with

RTC, Stop mode without RTC).

Some peripherals with wakeup capability can enable the HSI16 RC during Stop mode,

so as to get clock for processing the wakeup event. The main regulator remains active

in Stop 0 mode while it is turned off in Stop 1 mode.

• Standby mode

The Standby mode is used to achieve the lowest power consumption, with POR/PDR

always active in this mode. The main regulator is switched off to power down V

CORE

domain. The low-power regulator is either switched off or kept active. In the latter case,

DS12232 Rev 2 19/136

STM32G071x8/xB Functional overview

it only supplies SRAM to ensure data retention. The PLL, as well as the HSI16 RC

oscillator and the HSE crystal oscillator are also powered down. The RTC can remain

active (Standby mode with RTC, Standby mode without RTC).

For each I/O, the software can determine whether a pull-up, a pull-down or no resistor

shall be applied to that I/O during Standby mode.

Upon entering Standby mode, register contents are lost except for registers in the RTC

domain and standby circuitry. The SRAM contents can be retained through register

setting.

The device exits Standby mode upon external reset event (NRST pin), IWDG reset

event, wakeup event (WKUP pin, configurable rising or falling edge) or RTC event

(alarm, periodic wakeup, timestamp, tamper), or when a failure is detected on LSE

(CSS on LSE).

• Shutdown mode

The Shutdown mode allows to achieve the lowest power consumption. The internal

regulator is switched off to power down the V

CORE

domain. The PLL, as well as the

HSI16 and LSI RC-oscillators and HSE crystal oscillator are also powered down. The

RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC).

The BOR is not available in Shutdown mode. No power voltage monitoring is possible

in this mode. Therefore, switching to RTC domain is not supported.

SRAM and register contents are lost except for registers in the RTC domain.

The device exits Shutdown mode upon external reset event (NRST pin), IWDG reset

event, wakeup event (WKUP pin, configurable rising or falling edge) or RTC event

(alarm, periodic wakeup, timestamp, tamper).

3.7.5 Reset mode

During and upon exiting reset, the schmitt triggers of I/Os are disabled so as to reduce

power consumption. In addition, when the reset source is internal, the built-in pull-up

resistor on NRST pin is deactivated.

3.7.6 VBAT operation

The V

BAT

power domain, consuming very little energy, includes RTC, and LSE oscillator and

backup registers.

In VBAT mode, the RTC domain is supplied from VBAT pin. The power source can be, for

example, an external battery or an external supercapacitor. Two anti-tamper detection pins

are available.

The RTC domain can also be supplied from VDD/VDDA pin.

By means of a built-in switch, an internal voltage supervisor allows automatic switching of

RTC domain powering between V

and voltage from VBAT pin to ensure that the supply

voltage of the RTC domain (V

BAT

) remains within valid operating conditions. If both voltages

are valid, the RTC domain is supplied from VDD/VDDA pin.

An internal circuit for charging the battery on VBAT pin can be activated if the V

voltage is

within a valid range.

Note: External interrupts and RTC alarm/events cannot cause the microcontroller to exit the VBAT

mode, as in that mode the V

is not within a valid range.

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