ARM架构下的NEVE：优化嵌套虚拟化提升云计算性能

需积分: 23 166 浏览量更新于2024-07-18 收藏 603KB PDF 举报

"NEVE：Nested Virtualization Extensions for ARM" NEVE（Nested Virtualization Extensions for ARM）是一个重要的技术发展，针对的是在ARM架构上实现嵌套虚拟化的支持。随着ARM处理器在云计算基础设施中的广泛应用，尤其是在云服务提供商的服务器部署中，对能够运行多层虚拟机（VMs）的需求日益增长。传统的多核处理器架构通常依赖于x86架构的嵌套虚拟化能力，然而，ARM作为另一种主流架构，也面临着引入此类功能的挑战。 ARM先前的非嵌套虚拟化支持存在一定的限制，这导致在实际应用中性能不如x86平台。问题的关键在于，ARM的非嵌套虚拟化支持可能存在额外的陷阱，这些陷阱会频繁地将控制权交还给hypervisor（虚拟机监控程序），从而影响性能。为了克服这一问题，NEVE的研究团队——来自哥伦比亚大学和ARM公司——开发了首个利用ARM嵌套虚拟化特性的hypervisor。 NEVE的设计旨在解决ARM架构上的性能瓶颈，通过引入一种新颖的paravirtualization（半虚拟化）技术。这种技术允许开发者快速原型化和测试潜在的硬件改进，减少与底层硬件的交互，从而提升虚拟机的执行效率。paravirtualization方法能够在不牺牲安全性前提下，提供更流畅的虚拟环境，使得VM内部的性能接近于裸金属执行，这对于多层虚拟化的场景尤其重要。尽管ARM和x86在嵌套虚拟化方面的设计初衷相似，但由于硬件特性、指令集和优化的不同，NEVE的解决方案需要针对ARM的独特性进行定制。这意味着开发者需要深入了解ARM架构的特性，才能充分利用NEVE的优势，同时避免或减小性能损失。 NEVE代表了ARM生态系统在应对虚拟化需求方面的重要进步，它不仅提供了嵌套虚拟化的支持，而且还在性能优化和适应性设计方面进行了创新。这对于推动ARM服务器在云计算领域的发展具有重要意义，并可能开启一个新的技术创新时代，使得ARM成为构建高效、可扩展的多层虚拟化基础设施的强大平台。"

SOSP ’17, October 28, 2017, Shanghai, China Jin Tack Lim, Christoer Dall, Shih-Wei Li, Jason Nieh, and Marc Zyngier

3 PARAVIRTUALIZATION FOR

ARCHITECTURE EVALUATION

Unfortunately, ARMv8.3 hardware is not available, and the

newest publicly available ARM hardware is still v8.0. As

architectural support for virtualization is increasingly com-

mon, understanding the performance of these features is

important, ideally before they become set in production hard-

ware. However, evaluating new architecture features for vir-

tualization is challenging because of costs associated with

prototyping new hardware and the need to understand the

interaction of both hardware and software. Chip vendors use

cycle-accurate simulators to measure performance, but they

are typically many orders of magnitude slower than real hard-

ware, making it hard to evaluate real-life workloads. Booting

a full virtualization stack including the hypervisor and VM

can take days, and even then, measuring key application per-

formance characteristics such as fast I/O performance using

10G Ethernet is still not possible. Furthermore, simulators of

commercial architecture designs are themselves quite com-

plex to build and often closed and proprietary, limiting their

availability in practice. Software developers often can only

use simpler architecture models before hardware is available,

at the cost of not being able to measure any real architecture

performance.

To overcome this challenge, we introduce an existing idea,

paravirtualization, in a new context. Paravirtualization al-

lows for a software interface to a VM that diers slightly

from the underlying hardware [

]. It is used to make hy-

pervisors simpler and faster by avoiding certain architecture

features that are complex or dicult to virtualize eciently.

We instead use paravirtualization to allow us to build hy-

pervisors using new architecture features that do not exist

on current hardware, and measure the performance of a full

virtualization stack using new architecture features at native

execution speeds on existing hardware.

Paravirtualization to evaluate new architecture features is

only possible when the performance and functionality of the

proposed feature can be closely emulated using instructions

supported by available hardware. For core virtualization sup-

port in the architecture, changes often involve traps; either

by adding features to trap on instructions that previously

did not trap, or by adding logic to avoid costly traps. In

both cases, paravirtualization can be used to replace instruc-

tions inside the VM with other ones supported by available

hardware such that the resulting behavior and performance

closely mimic that of a proposed architectural change.

For example, as discussed in Section 2, current ARM server

hardware does not support nested virtualization, because

when a hypervisor runs inside a VM on top of another hy-

pervisor, various instructions that it executes do not trap to

the underlying hypervisor for proper execution, but instead

simply fail improperly. However, if we replace those hyper-

visor instructions with instructions that do trap on current

hardware and the trap cost is expected to remain similar in

future hardware, we can obtain similar relative performance

to future hardware that supports nested virtualization with

correct trapping behavior.

There are a couple key assumptions in this example. First,

the approach is useful for evaluating the relative performance

of an architecture feature compared to something else, not

to estimate absolute performance of future hardware. For

example, the approach can provide an accurate evaluation

of the overhead of nested virtualization compared to native

execution.

Second, the approach assumes that certain types of traps

are interchangeable in terms of performance. For example, on

ARM, the trap cost using an explicit trap instruction should

be similar to the cost of any system register access instruction

that traps. Only the cost of the trap itself needs to remain

similar; the overall cost of handling the respective trap can

be quite dierent. This assumption is likely to be true in

most cases and we have validated it on ARM hardware, as

discussed in Section 5.

Using this approach, it becomes possible to eciently eval-

uate the performance of full virtualization stacks interacting

with fast I/O peripherals, using many CPU cores, and with

real-world workloads. It avoids the extremely slow perfor-

mance, complexity, and limited availability of cycle-accurate

simulators for recent architecture versions of commercial

CPUs. Perhaps more importantly, the approach allows co-

design and rapid prototyping of software and architecture

together, reducing long feedback loops common today when

the performance of full software stacks is not known until

full OS support and hardware is released, which is long after

the architecture design phase takes place.

4 KVM/ARM NESTED VIRTUALIZATION

FOR ARMV8.3

Because ARMv8.3 hardware is not yet available, we leverage

our paravirtualization approach discussed in Section 3 to

allow us to design, implement, and evaluate the rst ARM

hypervisor to support nested virtualization using ARMv8.3

architectural support on existing ARMv8.0 hardware. Since

both ARM and x86 provide a single level of architectural

virtualization support, we take an approach similar to Tur-

tles [

] for supporting nested virtualization on x86, where

multiple levels of virtualization are multiplexed onto the sin-

gle level of architectural support available. We have imple-

mented nested virtualization support on ARM by modifying

KVM/ARM [

], the widely-used mainline Linux ARM hy-

pervisor. There are two kinds of modications: (1) changes

to KVM/ARM as a host hypervisor to support running guest

204

剩余16页未读，继续阅读

我是阿拉琳

粉丝: 0
资源: 1

ARM架构下的NEVE：优化嵌套虚拟化提升云计算性能

ARM Virtualization: Performance and Architectural Implication

virtualization

把字符中的所有大写字母转换成小写字母对字符中偶数位置的数据进行逆序输出

报错' MySchool' is defined but neve r 报错：已声明“MySchool”，但从未读取其值

idea好用的白皮肤

VSCode 中GO语言main有红色下划线

给我推荐20个wordpress开源主题，排行顺序由热度递减排序

javaweb项目进销存管理系统springboot+vue+redis idea导入 mysql数据库-java课程设计毕业设

毕业设计论文SpringBoot助学兼职系统.docx

毕业设计论文SpringBoot智能菜谱推荐系统.docx

最新资源