TMS320VC5509A DSP芯片手册：修订与功能更新

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TMS320VC5509A是一款专为数字信号处理（DSP）设计的固定点处理器芯片手册，文献编号为SPRS205K，最初发布于2002年11月，并在2008年1月进行了修订。该手册详细介绍了该处理器的各种特性、功能以及设计细节。 1. **技术更新**: - 在SPRS205J到SPRS205K的修订过程中，最关键的技术更改包括更新了第20页的Table 2-3中的信号描述。原描述为“数据总线保持器在复位时被禁用”，在修订后的版本中改为“数据总线保持器在复位时启用”。这可能涉及到硬件配置或指令行为的优化。 2. **目录与内容概览**: - 手册分为多个章节，第一章“TMS320VC5509A特性和概述”介绍了处理器的核心特性，包括但不限于性能指标和应用领域。 - 第二章“介绍”涵盖了芯片的总体描述和引脚分配。其中： - 2.1 芯片描述部分详细说明了芯片的功能定位、工作原理以及其在信号处理任务中的角色。 - 2.2 引脚分配分为GH和ZHHPackages（可能指的是封装类型）的终端分配，以及PGE封装的详细布局，这对于硬件工程师理解和连接电路至关重要。 - 2.3 可能还讨论了接口标准、电源管理和其他与外部设备交互的细节。 3. **版本历史**: - 修订历史表明，这份文档的关注点在于确保技术内容的准确性，每次修订都可能涉及对之前错误的修正、新功能的添加或文档结构的改进，以适应用户的需求和市场变化。 4. **适用范围**: TMS320VC5509A DSP芯片适用于各种信号处理应用，可能包括音频处理、通信系统、控制系统等，需要精确的算术运算和高速数据处理能力。 TMS320VC5509A PDF文档是开发人员、系统集成者和硬件工程师的重要参考资料，提供了关于该特定DSP芯片的深入理解，帮助他们充分利用其性能并解决设计中的问题。随着文档的更新，确保始终遵循最新修订以获得最佳性能和兼容性。

Introduction

November 2002 − Revised January 2008SPRS205K

Table 2−1. Pin Assignments for the GHH and ZHH Packages

BALL # SIGNAL NAME BALL #

SIGNAL

NAME

BALL #

SIGNAL

NAME

BALL #

SIGNAL

NAME

A2 V

D5 GPIO5 H2 DV

L13 D15

A3 GPIO4 D6 DR0 H3 A19 L14 CV

A4 DV

D7 S10 H4 C4 M1 C10

A5 FSR0 D8 S11 H5 C5 M2 C13

A6 CV

D9 DV

H10 DV

M3 V

A7 S12 D10 S25 H11 A’[0] M4 CV

A8 DV

D11 V

H12 RESET M5 V

A9 S20 D12 AIN2 H13 SDA M6 A5

A10 S21 D13 AIN1 H14 SCL M7 A1

A11 S23 D14 AIN0 J1 C6 M8 A15

A12 RTCINX1 E1 GPIO1 J2 DV

M9 D3

A13 RDV

E2 GPIO2 J3 C7 M10 D6

A14 RDV

E3 DV

J4 C8 M11 CV

B1 V

E4 V

J5 CV

M12 DV

B2 CV

E5 V

J10 CV

M13 V

B3 GPIO3 E6 DV

J11 CV

M14 D12

B4 TIN/TOUT0 E7 DX0 J12 TRST N1 V

B5 CLKR0 E8 S15 J13 TCK N2 V

B6 FSX0 E9 S13 J14 TMS N3 A13

B7 CV

E10 NC K1 A18 N4 A10

B8 CV

E11 AIN3 K2 C9 N5 A7

B9 V

E12 ADV

K3 C11 N6 DV

B10 S24 E13 V

K4 V

N7 CV

B11 V

E14 XF K5 V

N8 CV

B12 RTCINX2 F1 X1 K6 A3 N9 V

B13 RDV

F2 X2/CLKIN K7 A2 N10 V

B14 AV

F3 GPIO0 K8 D1 N11 D8

C1 PU F4 V

K9 A14 N12 D11

C2 V

F5 CLKOUT K10 DV

N13 DV

C3 NC F10 ADV

K11 EMU0 N14 V

C4 GPIO6 F11 V

K12 EMU1/OFF P1 V

C5 V

F12 INT4 K13 TDO P2 V

C6 CLKX0 F13 DV

K14 TDI P3 A12

C7 V

F14 INT3 L1 CV

P4 A9

C8 S14 G1 CV

L2 C14 P5 A17

C9 S22 G2 C1 L3 C12 P6 A4

C10 CV

G3 A20 L4 A11 P7 A16

C11 V

G4 C2 L5 A8 P8 DV

C12 RCV

G5 C0 L6 A6 P9 D2

C13 AV

G10 INT2 L7 A0 P10 D5

C14 AV

G11 USBPLLV

L8 D0 P11 D7

D1 GPIO7 G12 USBPLLV

L9 D4 P12 D10

D2 USBV

G13 INT1 L10 D9 P13 DV

D3 DN G14 INT0 L11 D13 P14 DV

D4 DP H1 C3 L12 D14

Introduction

November 2002 − Revised January 2008 SPRS205K

2.3 Signal Descriptions

Table 2−3 lists each signal, function, and operating mode(s) grouped by function. See Section 2.2 for pin

locations based on package type.

Table 2−3. Signal Descriptions

TERMINAL

NAME

MULTIPLEXED

SIGNAL NAME

I/O/Z

†

FUNCTION BK

‡

RESET

CONDITION

PARALLEL BUS

A[13:0] I/O/Z

A subset of the parallel address bus A13−A0 of the C55x DSP core

bonded to external pins. These pins serve in one of three functions: HPI

address bus (HPI.HA[13:0]), EMIF address bus (EMIF.A[13:0]), or

general-purpose I/O (GPIO.A[13:0]). The initial state of these pins

depends on the GPIO0 pin. See Section 3.5.1 for more information.

The address bus has a bus holder feature that eliminates passive

component requirement and the power dissipation associated with them.

The bus holders keep the address bus at the previous logic level when the

bus goes into a high-impedance state.

GPIO0 = 1:

HPI.HA[13:0] I

HPI address bus. HPI.HA[13:0] is selected when the Parallel Port Mode bit

field of the External Bus Selection Register is 10. This setting enables the

HPI in non-multiplexed mode.

HPI.HA[13:0] provides DSP internal memory access to host. In

non-multiplexed mode, these signals are driven by an external host as

address lines.

GPIO0 = 1:

Output,

EMIF.A[13:0]

GPIO0 = 0:

EMIF.A[13:0] O/Z

EMIF address bus. EMIF.A[13:0] is selected when the Parallel Port Mode

bit field of the External Bus Selection Register is 01. This setting enables

the full EMIF mode and the EMIF drives the parallel port address bus. The

internal A[14] address is exclusive-ORed with internal A[0] address and

the result is routed to the A[0] pin.

Input,

HPI.HA[13:0]

GPIO.A[13:0] I/O/Z

General-purpose I/O address bus. GPIO.A[13:0] is selected when the

Parallel Port Mode bit field of the External Bus Selection Register is 11.

This setting enables the HPI in multiplexed mode with the Parallel Port

GPIO register controlling the parallel port address bus. GPIO is also

selected when the Parallel Port Mode bit field is 00, enabling the Data

EMIF mode.

A′[0]

(BGA only)

EMIF.A′[0] O/Z

EMIF address bus A′[0]. This pin is not multiplexed with EMIF.A[14] and is

used as the least significant external address pin on the BGA package.

Output

†

I = Input, O = Output, S = Supply, Hi-Z = High-impedance

‡

BK = bus keeper (the bus keeper maintains the previous voltage level during reset or while the output pin is not driven), PU = pullup,

PD = pulldown, H = hysteresis input buffer, FS = fail-safe buffer

Introduction

November 2002 − Revised January 2008SPRS205K

Table 2−3. Signal Descriptions (Continued)

TERMINAL

NAME

RESET

CONDITION

‡

FUNCTIONI/O/Z

†

MULTIPLEXED

SIGNAL NAME

PARALLEL BUS (CONTINUED)

A[15:14]

(BGA only)

I/O/Z

A subset of the parallel address bus A15−A14 of the C55x DSP core

bonded to external pins. These pins serve in one of two functions: EMIF

address bus (EMIF.A[15:14]), or general-purpose I/O (GPIO.A[15:14]).

The initial state of these pins depends on the GPIO0 pin. See Section 3.5.1

for more information.

The address bus has a bus holder feature that eliminates passive

component requirement and the power dissipation associated with them.

The bus holders keep the address bus at the previous logic level when the

bus goes into a high-impedance state.

GPIO0 = 1:

Output,

EMIF.A[15:14]

EMIF.A[15:14] O/Z

EMIF address bus. EMIF.A[15:14] is selected when the Parallel Port Mode

bit field of the External Bus Selection Register is 01. This setting enables

the full EMIF mode and the EMIF drives the parallel port address bus.

GPIO0 = 0:

Input,

GPIO.A[15:14]

GPIO.A[15:14] I/O/Z

General-purpose I/O address bus. GPIO.A[15:14] is selected when the

Parallel Port Mode bit field of the External Bus Selection Register is 11.

This setting enables the HPI in multiplexed mode with the Parallel Port

GPIO register controlling the parallel port address bus. GPIO is also

selected when the Parallel Port Mode bit field is 00, enabling the Data

EMIF mode.

GPIO.A[15:14]

A[20:16]

(BGA only)

EMIF.A[20:16] O/Z

EMIF address bus. At reset, these address pins are set as output.

NOTE: These pins only function as EMIF address pins and they are not

multiplexed for any other function.

Output

D[15:0] I/O/Z

A subset of the parallel bidirectional data bus D31−D0 of the C55x DSP

core. These pins serve in one of two functions: EMIF data bus

(EMIF.D[15:0]) or HPI data bus (HPI.HD[15:0]). The initial state of these

pins depends on the GPIO0 pin. See Section 3.5.1 for more information.

The data bus includes bus keepers to reduce the static power dissipation

caused by floating, unused pins. This eliminates the need for external bias

resistors on unused pins. When the data bus is not being driven by the

CPU, the bus keepers keep the pins at the logic level that was most

recently driven. (The data bus keepers are enabled at reset, and can be

enabled/disabled under software control.)

GPIO0 = 1:

Input,

EMIF.D[15:0]

GPIO0 = 0:

Input,

HPI.HD[15:0]

EMIF.D[15:0] I/O/Z

EMIF data bus. EMIF.D[15:0] is selected when the Parallel Port Mode bit

field of the External Bus Selection Register is 00 or 01.

HPI.HD[15:0]

HPI.HD[15:0] I/O/Z

HPI data bus. HPI.HD[15:0] is selected when the Parallel Port Mode bit

field of the External Bus Selection Register is 10 or 11.

†

I = Input, O = Output, S = Supply, Hi-Z = High-impedance

‡

BK = bus keeper (the bus keeper maintains the previous voltage level during reset or while the output pin is not driven), PU = pullup,

PD = pulldown, H = hysteresis input buffer, FS = fail-safe buffer

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