BCM2711外围设备文档：ARM可访问的外设详解

BCM2711

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"BCM2711-peripherals.pdf 是一份技术文档，主要介绍了BCM2711芯片上可由ARM安全访问的各种外围设备，包括定时器、中断控制器、GPIO（通用输入输出）、USB、PCM/I2S（脉冲编码调制/集成电路声音）、DMA（直接存储器访问）控制器、I2C（集成电路总线）主控器、SPI（串行外设接口）主控器、PWM（脉宽调制）和UART（通用异步收发传输器）。这份数据表的目的是为开发者提供足够的信息以便将操作系统移植到BCM2711平台。然而，并非所有外围设备都已完全文档化。还有部分外围设备是设计用来由其他组件控制的。文档由Broadcom Europe Ltd.在2012年首次发布，Raspberry Pi (Trading) Ltd.在2020年进行了更新。" BCM2711是一款高性能的系统级芯片，广泛应用于嵌入式系统和物联网设备中，特别是Raspberry Pi等单板计算机。该芯片包含了一系列用于处理不同任务的外围接口： 1. **定时器**：定时器是用于精确计时和调度的硬件模块，可以在预设的时间间隔后触发事件或中断。 2. **中断控制器**：中断控制器管理来自各种设备的中断请求，确保处理器能及时响应外部事件。 3. **GPIO**：GPIO接口允许芯片与外部设备进行双向数字通信，通过编程设置引脚为输入或输出模式。 4. **USB**：USB接口支持高速数据传输，用于连接键盘、鼠标、打印机、存储设备等外围设备。 5. **PCM/I2S**：这些接口用于音频数据的传输，常用于连接音频编解码器和数字音频设备。 6. **DMA控制器**：DMA控制器可以绕过CPU直接在内存和外设之间传输数据，提高数据传输效率。 7. **I2C主控器**：I2C是一种多设备串行总线，用于低速、低功耗的设备间通信。 8. **SPI主控器**：SPI接口支持高速全双工通信，适用于传感器、显示屏等高速数据交换的场合。 9. **PWM**：PWM用于生成模拟信号，常见应用包括LED亮度调节、电机速度控制等。 10. **UARTs**：UART接口用于异步串行通信，常见于串口调试和与其他设备的通信。文档还提到了地址映射、外围设备访问的内存顺序注意事项，以及如UART1、SPI1、SPI2等辅助设备的详细信息，包括它们的实现细节、寄存器描述和功能。例如，MiniUART是一个简化版的UART，适用于轻量级通信；而Universal SPI Master提供了两个SPI接口，支持长位流传输和中断功能。 BCM2711的文档还涵盖了BSC（Burst Serial Controller），可能是I2C协议的一个变种，用于与其他I2C兼容设备交互。每个外围设备部分都包含了对其工作原理、操作方式和相关寄存器的详细描述，这对于开发者理解和驱动这些硬件是至关重要的。这份文档是开发基于BCM2711平台的软件或硬件设计的重要参考资料，它提供了从底层硬件层面理解和操作这些外围设备所需的详细信息。对于想要移植操作系统或编写驱动程序的开发者来说，是不可或缺的工具。

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Receiver enable

If this bit is clear no new symbols will be accepted by the receiver. Any symbols in progress of reception will be

finished.

Transmitter enable

If this bit is clear no new symbols will be sent by the transmitter. Any symbols in progress of transmission will be

finished.

Auto flow control

Automatic flow control can be enabled independent for the receiver and the transmitter.

CTS auto flow control impacts the transmitter only. The transmitter will not send out new symbols when the CTS line is

de-asserted. Any symbols in progress of transmission when the CTS line becomes de-asserted will be finished.

RTS auto flow control impacts the receiver only. In fact the name RTS for the control line is incorrect and should be RTR

(Ready to Receive). The receiver will de-assert the RTS (RTR) line when its receive FIFO has a number of empty spaces

left. Normally 3 empty spaces should be enough.

If looping back a mini UART using full auto flow control the logic is fast enough to allow the RTS auto flow level of '10' (De-

assert RTS when the receive FIFO has 1 empty space left).

Auto flow polarity

To offer full flexibility the polarity of the CTS and RTS (RTR) lines can be programmed. This should allow the mini

UART to interface with any existing hardware flow control available.

AUX_MU_STAT_REG Register

Description

The AUX_MU_STAT_REG provides a lot of useful information about the internal status of the mini UART not found on

a normal 16550 UART.

Table 14.

AUX_MU_STAT_REG

Bits Name Description Type Reset

31:28 Reserved. - - -

27:24 Transmit FIFO fill

level

These bits shows how many symbols are stored in the

transmit FIFO

The value is in the range 0-8

RO 0x0

23:20 Reserved. - - -

19:16 Receive FIFO fill

level

These bits shows how many symbols are stored in the

receive FIFO

The value is in the range 0-8

RO 0x0

15:10 Reserved. - - -

9 Transmitter done This bit is set if the transmitter is idle and the transmit FIFO

is empty.

It is a logic AND of bits 3 and 8

RO 0x1

8 Transmit FIFO is

empty

If this bit is set the transmitter FIFO is empty. Thus it can

accept 8 symbols.

RO 0x1

7 CTS line This bit shows the status of the UART1_CTS line. RO 0x0

6 RTS status This bit shows the status of the UART1_RTS line. RO 0x0

5 Transmit FIFO is

full

This is the inverse of bit 1 RO 0x0

BCM2711 ARM Peripherals

2.2. Mini UART 15

Bits Name Description Type Reset

4 Receiver overrun This bit is set if there was a receiver overrun. That is: one or

more characters arrived whilst the receive FIFO was full.

The newly arrived characters have been discarded. This bit

is cleared each time the AUX_MU_LSR_REG register is read.

RO 0x0

3 Transmitter is idle If this bit is set the transmitter is idle.

If this bit is clear the transmitter is busy.

RO 0x1

2 Receiver is idle If this bit is set the receiver is idle.

If this bit is clear the receiver is busy.

This bit can change unless the receiver is disabled

RO 0x1

1 Space available If this bit is set the mini UART transmitter FIFO can accept

at least one more symbol.

If this bit is clear the mini UART transmitter FIFO is full

RO 0x0

0 Symbol available If this bit is set the mini UART receive FIFO contains at

least 1 symbol

If this bit is clear the mini UART receiver FIFO is empty

RO 0x0

Receiver is idle

This bit is only useful if the receiver is disabled. The normal use is to disable the receiver, then check (or wait) until the

bit is set. Now you can be sure that no new symbols will arrive (e.g. now you can change the baudrate…).

Transmitter is idle

This bit tells if the transmitter is idle. Note that the bit will set only for a short time if the transmit FIFO contains data.

Normally you want to use bit 9: Transmitter done.

RTS status

This bit is useful only in receive Auto flow-control mode as it shows the status of the RTS line.

AUX_MU_BAUD_REG Register

Description

The AUX_MU_BAUD_REG register allows direct access to the 16-bit wide baudrate counter.

Table 15.

AUX_MU_BAUD_REG

Bits Name Description Type Reset

31:16 Reserved. - - -

15:0 Baudrate mini UART baudrate counter RW 0x0000

This is the same register as is accessed using the DLAB bit and the first two registers, but much easier to access.

2.3. Universal SPI Master (2x)

The two universal SPI masters are secondary low throughput SPI interfaces. Like the mini UART the devices need to be

enabled before they can be used.

BCM2711 ARM Peripherals

2.3. Universal SPI Master (2x) 16

If the system clock is 250 MHz and the speed field is zero the SPI clock frequency is 125 MHz. The practical SPI clock will

be lower as the I/O pads can not transmit or receive signals at such high speed. The lowest SPI clock frequency with a

250 MHz system clock is 30.5 KHz.

The hardware has an option to add hold time to the MOSI signal against the SPI clk. This is again done using the system

clock. So a 250 MHz system clock will add hold times in units of 4 ns. Hold times of 0, 1, 4 and 7 system clock cycles can

be used. (So at 250MHz an additional hold time of 0, 4, 16 and 28 ns can be achieved). The hold time is additional to the

normal output timing as specified in the data sheet.

2.3.2. Interrupts

The SPI block has two interrupts: TX FIFO is empty, SPI is Idle.

TX FIFO is empty

This interrupt will be asserted as soon as the last entry has been read from the transmit FIFO. At that time the

interface will still be busy shifting out that data. This also implies that the receive FIFO will not yet contain the last

received data. It is possible at that time to fill the TX FIFO again and read the receive FIFO entries which have been

received. There is a RX FIFO level field which tells you exactly how many words are in the receive FIFO. In general at

that time the receive FIFO should contain the number of TX items minus one (the last one still being received). Note

that there is no "receive FIFO full" interrupt as the number of entries received can never be more than the number of

entries transmitted.

SPI is Idle

This interrupt will be asserted when the transmit FIFO is empty and the SPI block has finished all actions (including

the CS-high time). By this time the receive FIFO will have received all data as well.

2.3.3. Long bit streams

The SPI module works in bursts of up to 32 bits. Some SPI devices require data which is longer than 32 bits. To do this

the user must make use of the two different data TX addresses: TX data written to one address causes the CS to remain

asserted. TX data written to the other address causes the CS to be de-asserted at the end of the transmit cycle. So in

order to exchange 96 bits you do the following:

Write the first two data words to one address, then write the third word to the other address.

2.3.4. SPI register details

AUX_SPI1_CNTL0_REG, AUX_SPI2_CNTL0_REG Registers

Description

The AUX_SPIx_CNTL0_REG registers control many features of the SPI interfaces.

Table 16.

AUX_SPI1_CNTL0_REG

AUX_SPI2_CNTL0_REG

Registers

Bits Name Description Type Reset

31:20 Speed Sets the SPI clock speed. spi_clk_freq =

system_clock_freq/2*(speed+1)

RW 0x000

19:17 Chip Selects The pattern output on the CS pins when active. RW 0x7

16 Post-input mode If set the SPI input works in post-input mode.

For details see text further down

RW 0x0

15 Variable CS If 1 the SPI takes the CS pattern and the data from the TX

FIFO

If 0 the SPI takes the CS pattern from bits 17-19 of this

Set this bit only if bit 14 (variable width) is also set

RW 0x0

BCM2711 ARM Peripherals

2.3. Universal SPI Master (2x) 18

Bits Name Description Type Reset

14 Variable width If 1 the SPI takes the shift length and the data from the TX

FIFO

If 0 the SPI takes the shift length from bits 0-5 of this

RW 0x0

13:12 DOUT Hold time Controls the extra DOUT hold time in system clock cycles.

00 : No extra hold time

01 : 1 system clock extra hold time

10 : 4 system clocks extra hold time

11 : 7 system clocks extra hold time

RW 0x0

11 Enable Enables the SPI interface. Whilst disabled the FIFOs can

still be written to or read from

This bit should be 1 during normal operation.

RW 0x0

10 In rising If 1 data is clocked in on the rising edge of the SPI clock

If 0 data is clocked in on the falling edge of the SPI clock

RW 0x0

9 Clear FIFOs If 1 the receive and transmit FIFOs are held in reset (and

thus flushed.)

This bit should be 0 during normal operation.

RW 0x0

8 Out rising If 1 data is clocked out on the rising edge of the SPI clock

If 0 data is clocked out on the falling edge of the SPI clock

RW 0x0

7 Invert SPI CLK If 1 the 'idle' clock line state is high.

If 0 the 'idle' clock line state is low.

RW 0x0

6 Shift out MS bit

first

If 1 the data is shifted out starting with the MS bit. (bit 31 or

bit 23)

If 0 the data is shifted out starting with the LS bit. (bit 0)

RW 0x0

5:0 Shift length Specifies the number of bits to shift

This field is ignored when using 'variable width' mode

RW 0x00

Invert SPI CLK

Changing this bit will immediately change the polarity of the SPI clock output. It is recommended to not do this when

the CS is active, as the connected devices will see this as a clock change.

DOUT hold time

Because the interface runs off fast silicon the MOSI hold time against the clock will be very short. This can cause

considerable problems on SPI slaves. To make it easier for the slave to see the data the hold time of the MOSI out

against the SPI clock out is programmable.

Variable width

In this mode the shift length is taken from the transmit FIFO. The transmit data bits 28:24 are used as shift length and

the data bits 23:0 are the actual transmit data. If the option 'shift MS out first' is selected the first bit shifted out will be

bit 23. The receive data will arrive as normal.

BCM2711 ARM Peripherals

2.3. Universal SPI Master (2x) 19

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