JEDEC ESD JS-002-2022: 电静电放电敏感度测试标准

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"JEDEC ESD JS-002-2022 是一份由 Electrostatic Discharge Association (ESDA) 和 JEDEC Solid State Technology Association 共同制定的美国国家标准，用于静电放电敏感性测试 - 充电设备模型 (Charged Device Model, CDM) 的设备级别测试。这份标准是对 ANSI/ESDA/JEDEC JS-002-2018 的修订版，旨在为电子元器件提供静电防护和性能评估的统一规范。标准的目的是消除制造商和购买者之间的误解，促进产品的互换性和改进，并帮助购买者根据特定需求选择合适的产品。" 此文档详细描述了如何进行静电放电 (ESD) 敏感度测试，特别是针对充电设备模型的测试方法。CDM 测试是 ESD 测试的一种，它模拟了设备在制造、处理或使用过程中因接触带电物体而可能遭受的静电冲击情况。标准规定了测试条件、设备设置、测试程序以及合格标准，以确保电子设备在实际应用中的可靠性。测试内容可能包括但不限于以下几个方面： 1. **测试配置**：定义了测试装置的配置，包括充电板、测试探头和环境条件（如湿度和温度）。 2. **测试等级**：设定了多个能量等级的测试，以评估设备对不同强度静电冲击的耐受能力。 3. **测试步骤**：详细说明了如何对样品进行预处理、充电、接触和放电的过程，以及如何记录和分析结果。 4. **结果评估**：规定了如何根据测试结果判断设备是否符合标准要求，包括失效模式分析和性能阈值。 5. **设备分类**：依据测试结果，将设备分为不同的 ESD 敏感度等级，指导生产和设计过程中的静电防护措施。 6. **质量控制**：标准还可能涉及质量控制和持续改进的流程，确保测试的一致性和准确性。 7. **合规性**：对于电子行业，符合JEDEC和ESDA标准是产品进入市场前必须考虑的重要因素，因为它确保了产品的质量和安全性。此标准的更新，如 JS-002-2022 版本，通常会反映技术发展、新的测试方法或业界最佳实践，以适应不断变化的电子元器件和系统的需求。对于制造商来说，遵循这些标准有助于减少产品因ESD导致的故障，提高客户满意度，并减少召回和保修成本。对于买家而言，了解这些标准可以帮助他们选择符合安全和性能要求的产品。

ANSI/ESDA/JEDEC JS-002-2022

Contents

Page

vii

Annex I (Informative) Waveform Verification Procedures Using Factor/Offset and

Software Voltage Adjustment Methods

.........................................................................34

I.1 Factor/Offset Adjustment Method ......................................................................................34

I.2 Software Voltage Adjustment Method ...............................................................................37

I.3 Example Parameter Recording Tables ...............................................................................41

Annex J (Informative) Determining the Appropriate Charge Time (Delay) for Full

Charging of a Large Module or Device

.........................................................................42

J.1 Procedure for Charge Time (Delay) Determination .........................................................42

Annex K (Informative) Bibliography ...............................................................................................44

Annex L (Informative) Revision History for ANSI/ESDA/JEDEC JS-002 ............................45

L.1 Joint Document Summary ....................................................................................................45

L.2 ANSI/ESDA/JEDEC JS-002-2014: Summary by Clause ..............................................45

L.3 ANSI/ESDA/JEDEC JS-002-2018: Summary by Clause ..............................................46

L.4 ESDA/JEDEC JWIP-002-2021: Summary by Clause ....................................................46

Figures Page

Figure 1 — Simplified CDM Tester Hardware Schematic ............................................................. 4

Figure 2 — CDM Characteristic Positive/Negative Waveforms and Parameters ......................... 12

Figure 3 — Verification Module Thickness, Flatness, Dishing, and Doming Illustrations .......... 20

Figure 4 — Simplified CDM Tester Electrical Schematic ............................................................ 28

Figure 5 — Sample Waveforms from a 1 GHz Oscilloscope ....................................................... 28

Figure 6 — Sample Waveforms from an 8 GHz Oscilloscope ..................................................... 28

Figure 7 — Single Discharge Procedure (Field Charging, I

CDM

Pulse, and Slow Discharge) ....... 32

Figure 8 — Dual Discharge Procedure ......................................................................................... 33

Figure 9 — Example of a Waveform Verification Flow for Qualification and Quarterly Checks

Using the Factor/Offset Adjustment Method ............................................................ 35

Figure 10 — Example of a Waveform Verification Flow for the Routine Checks ....................... 36

Figure 11 — Example of the Impact of Factor Adjustment on the Average Ip for the Large

Verification Module High Bandwidth Oscilloscope ................................................ 37

Figure 12 — Example of a Waveform Verification Flow for Qualification and Quarterly Checks

Using the Software Voltage Adjustment Method .................................................... 39

Figure 13 — Example of a Waveform Verification Flow for the Routine Checks ....................... 40

Figure 14 — Example Characterization of Charge Time (Delay) Versus Ip ................................ 43

Tables Page

Table 1 — CDM Waveform Characteristics for a 1 GHz Bandwidth Oscilloscope ..................... 11

Table 2 — CDM Waveform Characteristics for a High Bandwidth (≥ 6 GHz) Oscilloscope ...... 11

Table 3 — CDM ESDS Device Classification Levels .................................................................. 18

Table 4 — Specification for CDM Tester Verification Modules (Metal Discs) ........................... 19

Table 5 — Inclusion of Lower ESD Level High-Speed Pin Data ................................................. 25

Table 6 — Example Waveform Parameter Recording Table for the Factor/Offset Adjustment

Method ......................................................................................................................... 41

Table 7 — Example Waveform Parameter Recording Table for the Software Voltage Adjustment

Method ......................................................................................................................... 41

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JEDEC

ANSI/ESDA/JEDEC JS-002-2022

Page 1

Test Method JS-002-2022

(Revision of Test Method JS-002-2018)

CHARGED DEVICE MODEL (CDM)

DEVICE LEVEL

(From Board Ballot JCB-22-08 jointly formulated under the cognizance of the JC-14.1 Subcommittee on

Reliability Test Methods for Packaged Devices and the ESDA Standards Committee.)

1 Scope

This document establishes the procedure for testing, evaluating, and classifying devices and

microcircuits according to their susceptibility (sensitivity) to damage or degradation by exposure

to a defined field-induced charged device model (CDM) electrostatic discharge (ESD). All

packaged semiconductor devices, thin-film circuits, surface acoustic wave (SAW) devices,

optoelectronic devices, hybrid integrated circuits (HICs), and multi-chip modules (MCMs)

containing any of these devices are to be evaluated according to this standard. The devices shall be

assembled into a package similar to that expected in the final application to perform the tests. This

CDM document does not apply to socketed discharge model testers.

The purpose (objective) of this document is to establish a test method that will replicate CDM

failures and provide reliable, repeatable CDM ESD test results from tester to tester, regardless of

device type. Repeatable data will allow accurate classifications and comparisons of CDM ESD

sensitivity levels.

2 Normative References

Unless otherwise specified, the following documents of the latest issue, revision, or amendment

form a part of this standard to the extent specified herein:

ESD ADV1.0. ESD Association Glossary of Terms

JESD99, JEDEC Standard - Terms, Definitions, and Letter Symbols for Microelectronic Devices

JESD88, Dictionary of Terms for Solid-State Technology

JESD625, Requirements for Handling Electrostatic Discharge-Sensitive (ESDS) Devices

ANSI/ESD S20.20, Protection of Electrical and Electronic Parts, Assemblies and Equipment

(Excluding Electrically Initiated Explosive Devices)

IEC61340-5-1 – Electrostatics – Part 5-1: Protection of Electronic Devices from Electrostatic

Phenomena – General Requirements

EOS/ESD Association, Inc., 7900 Turin Road, Bldg. 3, Rome, NY 13440-2069; 315-339-6937;

www.esda.org

JEDEC Global Standards for the Microelectronics Industry; www.jedec.org

IEC – International Electrotechnical Commission, www.iec.ch

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