N25Q128 - 3 V
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2
2.1
2.2
2.3
2.4
信号描述
信号描述
串行数据输出(DQ1)
该输出信号用于将数据串行传输出器件。数据在串行时钟(C)的下降沿移出。当用作输入时,
它锁存在串行时钟(C)的上升沿。
在扩展SPI协议中,在四路和双路输入快速程序(QIFP,DIFP)指令期间以及在四路和双路输
入扩展快速程序(QIEFP,DIEFP)指令期间,引脚DQ1也用作输入。
在双IOSPI协议(DIO-SPI)中,DQ1引脚始终充当输入输出。
在四IOSPI协议(QIO-SPI)中,DQ1引脚始终充当输入输出,但使用增强程序电源电压(VPP)执
行的程序或擦除周期除外。在这种情况下,设备暂时进入扩展SPI协议。一旦VPP引脚电压变
为低电平,协议就变为QIO-SPI。
串行数据输入(DQ0)
该输入信号用于将数据串行传输到设备中。它接收指令、地址和要编程的数据。值在串行时
钟(C)的上升沿锁存。数据在串行时钟(C)的下降沿移出。
在扩展SPI协议中,在四路和双路输出快速读取(QOFR,DOFR)和四路和双路输入输出快速读
取(QIOFR,DIOFR)指令期间,引脚DQ0也用作输入输出。
在DIO-SPI协议中,DQ0引脚始终充当输入输出。
在QIO-SPI协议中,DQ0引脚始终充当输入输出,但Vpp执行的程序或擦除周期除外。在这
种情况下,设备暂时进入扩展SPI协议。然后,一旦VPP引脚电压变为低电平,协议就会返
回到QIO-SPI。
串行时钟(C)
该输入信号为串行接口提供时序。串行数据输入端(DQ0)的指令、地址或数据在串行时钟(C)
的上升沿锁存。数据在串行时钟(C)的下降沿移出。
芯片选择
当该输入信号为高电平时,器件被取消选择,串行数据输出(dq1)处于高阻抗。除非内部程
序、擦除或写入状态寄存器周期正在进行中,否则器件将处于备用电源模式(这不是深度掉
电模式)。驱动芯片选择(s)低使能器件,将其置于有源功率模式。
上电后,在任何指令开始之前都需要一个片选下降沿。
趣卡翻译(fanyi.qukaa.com)
Signal descriptions N25Q128 - 3 V
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2 Signal descriptions
2.1 Serial data output (DQ1)
This output signal is used to transfer data serially out of the device. Data are shifted out on
the falling edge of Serial Clock (C). When used as an Input, It is latched on the rising edge
of the Serial Clock (C).
In the Extended SPI protocol, during the Quad and Dual Input Fast Program (QIFP, DIFP)
instructions and during the Quad and Dual Input Extended Fast Program (QIEFP, DIEFP)
instructions, pin DQ1 is used also as an input.
In the Dual I/O SPI protocol (DIO-SPI) the DQ1 pin always acts as an input/output.
In the Quad I/O SPI protocol (QIO-SPI) the DQ1 pin always acts as an input/output, with the
exception of the Program or Erase cycle performed with the Enhanced Program Supply
Voltage (VPP). In this case the device temporarily goes in Extended SPI protocol. The
protocol then becomes QIO-SPI as soon as the VPP pin voltage goes low.
2.2 Serial data input (DQ0)
This input signal is used to transfer data serially into the device. It receives instructions,
addresses, and the data to be programmed. Values are latched on the rising edge of Serial
Clock (C). Data are shifted out on the falling edge of the Serial Clock (C).
In the Extended SPI protocol, during the Quad and Dual Output Fast Read (QOFR, DOFR)
and the Quad and Dual Input/Output Fast Read (QIOFR, DIOFR) instructions, pin DQ0 is
also used as an input/output.
In the DIO-SPI protocol the DQ0 pin always acts as an input/output.
In the QIO-SPI protocol, the DQ0 pin always acts as an input/output, with the exception of
the Program or Erase cycle performed with the VPP. In this case the device temporarily
goes in Extended SPI protocol. Then, the protocol returns to QIO-SPI as soon as the VPP
pin voltage goes low.
2.3 Serial Clock (C)
This input signal provides the timing for the serial interface. Instructions, addresses, or data
present at serial data input (DQ0) are latched on the rising edge of Serial Clock (C). Data
are shifted out on the falling edge of the Serial Clock (C).
2.4 Chip Select (S)
When this input signal is high, the device is deselected and serial data output (DQ1) is at
high impedance. Unless an internal program, erase or write status register cycle is in
progress, the device will be in the standby power mode (this is not the deep power-down
mode). Driving Chip Select (S
) low enables the device, placing it in the active power mode.
After power-up, a falling edge on Chip Select (S
) is required prior to the start of any
instruction.