List of Figures
16
Tessent® Shell User’s Manual, v2020.3
Figure 5-29. Generate Graybox Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Figure 5-30. Run ATPG on the Core’s Internal Mode Example. . . . . . . . . . . . . . . . . . . . . . 203
Figure 5-31. Two-Pass Insertion Flow With Hybrid TK/LBIST. . . . . . . . . . . . . . . . . . . . . . 205
Figure 5-32. Two-Pass Insertion Flow for RTL, Wrapped Cores . . . . . . . . . . . . . . . . . . . . . 227
Figure 5-33. Two-Pass Insertion Flow for RTL, Top Level . . . . . . . . . . . . . . . . . . . . . . . . . 230
Figure 6-1. Integrated Tessent DFT Solution for Automotive . . . . . . . . . . . . . . . . . . . . . . . 244
Figure 6-2. Initial Design for Automotive Test Case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Figure 6-3. DFT Integration at the Core Level for Automotive . . . . . . . . . . . . . . . . . . . . . . 247
Figure 6-4. DFT Integration at the Top Level for Automotive . . . . . . . . . . . . . . . . . . . . . . . 248
Figure 6-5. DFT Insertion Flow for Automotive Test Case . . . . . . . . . . . . . . . . . . . . . . . . . 249
Figure 6-6. DFT Insertion Flow for processor_core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Figure 6-7. Enhanced Clocking and DFT Controls After Second DFT Insertion Pass. . . . . 256
Figure 6-8. ATPG Pattern Generation Flow for processor_core. . . . . . . . . . . . . . . . . . . . . . 262
Figure 6-9. DFT Insertion Flow for gps_baseband . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
Figure 6-10. Dofile Example for Top-Level Scan Chain Insertion, Automotive Flow. . . . . 286
Figure 7-1. TSDB Data Flow, Core Level, First Insertion Pass . . . . . . . . . . . . . . . . . . . . . . 291
Figure 7-2. TSDB Data Flow, Core Level, Second Insertion Pass . . . . . . . . . . . . . . . . . . . . 292
Figure 7-3. TSDB Data Flow, Core Level, Scan Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Figure 7-4. TSDB Data Flow, Core Level, Pattern Generation. . . . . . . . . . . . . . . . . . . . . . . 293
Figure 7-5. TSDB Data Flow, Top Level, First Insertion Pass . . . . . . . . . . . . . . . . . . . . . . . 295
Figure 7-6. TSDB Data Flow, Top Level, Second Insertion Pass. . . . . . . . . . . . . . . . . . . . . 296
Figure 7-7. TSDB Data Flow, Top Level, Scan Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
Figure 7-8. TSDB Data Flow, Top Level, ATPG Pattern Generation. . . . . . . . . . . . . . . . . . 298
Figure 7-9. TSDB Data Flow, Top Level, ATPG Pattern Generation with Pattern Retargeting
299
Figure 8-1. Example Chip with PLL Embedded Inside Lower Core . . . . . . . . . . . . . . . . . . 303
Figure 8-2. Active OCCs During Internal Test Modes of corec and coreb. . . . . . . . . . . . . . 304
Figure 8-3. Active OCCs During Internal Test Modes of corea and coreb. . . . . . . . . . . . . . 305
Figure 8-4. Active OCCs During Test Modes of Top Level . . . . . . . . . . . . . . . . . . . . . . . . . 306
Figure 8-5. Wrapped Core Boundary Scan Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
Figure 9-1. 200ns Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
Figure 9-2. Shift Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
Figure 9-3. Timing Diagram for Shift Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
Figure 9-4. Load_Unload Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
Figure 9-5. Timing Diagram for Load_Unload Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . 386
Figure 9-6. Shadow_Control Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
Figure 9-7. Master_Observe Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
Figure 9-8. Shadow_Observe Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
Figure 9-9. Sequential Transparent Circuitry Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
Figure 9-10. Skew_Load Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
Figure 9-11. Skew_load applied within Pattern. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
Figure 9-12. Full Ram Sequential Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
Figure 9-13. Full Clock Sequential Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
Figure 9-14. Init_force Procedure Usage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
Figure 10-1. Tessent Visualizer Default View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433