STM32L475超低功耗MCU数据手册：实现实时操作系统与高效能选项

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STM32L475xx是一款由STMicroelectronics生产的低功耗24位ARM Cortex-M4微控制器，集成了一款FPU（浮点运算单元），专为满足市场对低功耗应用的需求而设计。该产品于2018年4月进入生产阶段，并提供了详细的DS10969 Rev 4数据手册。这款微控制器的主要特点包括： 1. **超低功耗与灵活电源控制**：STM32L475支持宽范围的供电，从1.71V到3.6V，使其适应多种电池和电源环境。它能够在-40°C至85°C、105°C或125°C的温度范围内稳定工作。在超低功耗模式下，电池备份寄存器（RTC和32x32位）仅消耗300nA，而在待机模式（5个唤醒引脚）下降至30nA，甚至在带RTC的待机模式下也仅有420nA。停机模式（Stop 2）下消耗1.1μA，有RTC时为1.4μA，运行模式下则为100μA/MHz。 2. **高性能与能效**：STM32L475的Cortex-M4内核带有ART Accelerator，能够实现无等待状态的执行，最高频率可达80MHz。它的性能指标强大，如1.25 DMIPS/MHz（Drystone 2.1基准测试）和273.55 CoreMark分数（3.42 CoreMark/MHz @ 80MHz）。在能效方面，ULPMark™测试显示出出色的CP（控制处理）和PP（处理性能）得分，分别是295和101分。 3. **时钟源选项**：STM32L475支持4到48MHz的晶体振荡器，以及32kHz的晶振，为不同的应用场景提供了灵活的时钟配置。 4. **接口与功能**：该芯片集成了USB OTG FS（全速）接口，以及模拟和音频功能，使其适用于广泛的物联网（IoT）和消费电子设备。此外，它还具备Brownout reset（欠电压保护）功能，确保在电源波动时系统稳定。 5. **低功耗唤醒模式**：通过批处理获取模式（BAM），微控制器可以从停机模式快速唤醒，只需4μs。这使得设备能够在需要时迅速恢复操作，保持低功耗的同时提供高效的响应时间。 STM32L475xx是一款具有高度灵活性和能效优势的微控制器，适合于那些对低功耗、高性能和快速唤醒有严格要求的应用，如穿戴设备、智能家居、工业监控等。其广泛的电源支持、丰富的功能集和出色的能源管理能力使其在现代物联网设备开发中占有重要地位。

Functional overview STM32L475xx

16/203 DS10969 Rev 4

3 Functional overview

3.1 Arm

Cortex

-M4 core with FPU

The Arm

Cortex

-M4 with FPU processor is the latest generation of Arm

processors for

embedded systems. It was developed to provide a low-cost platform that meets the needs of

MCU implementation, with a reduced pin count and low-power consumption, while

delivering outstanding computational performance and an advanced response to interrupts.

The Arm

Cortex

-M4 with FPU 32-bit RISC processor features exceptional code-

efficiency, delivering the high-performance expected from an Arm

core in the memory size

usually associated with 8- and 16-bit devices.

The processor supports a set of DSP instructions which allow efficient signal processing and

complex algorithm execution.

Its single precision FPU speeds up software development by using metalanguage

development tools, while avoiding saturation.

With its embedded Arm

core, the STM32L475xx family is compatible with all Arm

tools

and software.

Figure 1 shows the general block diagram of the STM32L475xx family devices.

3.2 Adaptive real-time memory accelerator (ART Accelerator™)

The ART Accelerator™ is a memory accelerator which is optimized for STM32 industry-

standard Arm

Cortex

-M4 processors. It balances the inherent performance advantage of

the Arm

Cortex

-M4 over Flash memory technologies, which normally requires the

processor to wait for the Flash memory at higher frequencies.

To release the processor near 100 DMIPS performance at 80MHz, the accelerator

implements an instruction prefetch queue and branch cache, which increases program

execution speed from the 64-bit Flash memory. Based on CoreMark benchmark, the

performance achieved thanks to the ART accelerator is equivalent to 0 wait state program

execution from Flash memory at a CPU frequency up to 80 MHz.

3.3 Memory protection unit

The memory protection unit (MPU) is used to manage the CPU accesses to memory to

prevent one task to accidentally corrupt the memory or resources used by any other active

task. This memory area is organized into up to 8 protected areas that can in turn be divided

up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4

gigabytes of addressable memory.

The MPU is especially helpful for applications where some critical or certified code has to be

protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-

time operating system). If a program accesses a memory location that is prohibited by the

MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can

dynamically update the MPU area setting, based on the process to be executed.

The MPU is optional and can be bypassed for applications that do not need it.

DS10969 Rev 4 17/203

STM32L475xx Functional overview

3.4 Embedded Flash memory

STM32L475xx devices feature up to 1 Mbyte of embedded Flash memory available for

storing programs and data. The Flash memory is divided into two banks allowing read-

while-write operations. This feature allows to perform a read operation from one bank while

an erase or program operation is performed to the other bank. The dual bank boot is also

supported. Each bank contains 256 pages of 2

Kbyte.

Flexible protections can be configured thanks to option bytes:

• Readout protection (RDP) to protect the whole memory. Three levels are available:

– Level 0: no readout protection

– Level 1: memory readout protection: the Flash memory cannot be read from or

written to if either debug features are connected, boot in RAM or bootloader is

selected

– Level 2: chip readout protection: debug features (Cortex-M4 JTAG and serial

wire), boot in RAM and bootloader selection are disabled (JTAG fuse). This

selection is irreversible.

• Write protection (WRP): the protected area is protected against erasing and

programming. Two areas per bank can be selected, with 2-Kbyte granularity.

• Proprietary code readout protection (PCROP): a part of the flash memory can be

protected against read and write from third parties. The protected area is execute-only:

it can only be reached by the STM32 CPU, as an instruction code, while all other

accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited.

One area per bank can be selected, with 64-bit granularity. An additional option bit

(PCROP_RDP) allows to select if the PCROP area is erased or not when the RDP

protection is changed from Level 1 to Level 0.

Table 3. Access status versus readout protection level and execution modes

Area

Protection

level

User execution

Debug, boot from RAM or boot

from system memory (loader)

Read Write Erase Read Write Erase

Main

memory

1 Yes Yes Yes No No No

2 Yes Yes Yes N/A N/A N/A

System

memory

1 Yes No No Yes No No

2 Yes No No N/A N/A N/A

Option

bytes

1 Yes Yes Yes Yes Yes Yes

2 Yes No No N/A N/A N/A

Backup

registers

1YesYesN/A

(1)

1. Erased when RDP change from Level 1 to Level 0.

No No N/A

(1)

2 Yes Yes N/A N/A N/A N/A

SRAM2

1 Yes Yes Yes

(1)

No No No

(1)

2 Yes Yes Yes N/A N/A N/A

Functional overview STM32L475xx

18/203 DS10969 Rev 4

The whole non-volatile memory embeds the error correction code (ECC) feature supporting:

• single error detection and correction

• double error detection.

• The address of the ECC fail can be read in the ECC register

3.5 Embedded SRAM

STM32L475xx devices feature up to 128 Kbyte of embedded SRAM. This SRAM is split into

two blocks:

• 96 Kbyte mapped at address 0x2000 0000 (SRAM1)

• 32 Kbyte located at address 0x1000 0000 with hardware parity check (SRAM2).

This block is accessed through the ICode/DCode buses for maximum performance.

These 32 Kbyte SRAM can also be retained in Standby mode.

The SRAM2 can be write-protected with 1 Kbyte granularity.

The memory can be accessed in read/write at CPU clock speed with 0 wait states.

3.6 Firewall

The device embeds a Firewall which protects code sensitive and secure data from any

access performed by a code executed outside of the protected areas.

Each illegal access generates a reset which kills immediately the detected intrusion.

The Firewall main features are the following:

• Three segments can be protected and defined thanks to the Firewall registers:

– Code segment (located in Flash or SRAM1 if defined as executable protected

area)

– Non-volatile data segment (located in Flash)

– Volatile data segment (located in SRAM1)

• The start address and the length of each segments are configurable:

– Code segment: up to 1024 Kbyte with granularity of 256 bytes

– Non-volatile data segment: up to 1024 Kbyte with granularity of 256 bytes

– Volatile data segment: up to 96 Kbyte with a granularity of 64 bytes

• Specific mechanism implemented to open the Firewall to get access to the protected

areas (call gate entry sequence)

• Volatile data segment can be shared or not with the non-protected code

• Volatile data segment can be executed or not depending on the Firewall configuration

The Flash readout protection must be set to level 2 in order to reach the expected level of

protection.

DS10969 Rev 4 19/203

STM32L475xx Functional overview

3.7 Boot modes

At startup, BOOT0 pin and BOOT1 option bit are used to select one of three boot options:

• Boot from user Flash

• Boot from system memory

• Boot from embedded SRAM

The boot loader is located in system memory. It is used to reprogram the Flash memory by

using USART, I2C, SPI, CAN or USB OTG FS in Device mode through DFU (device

firmware upgrade).

3.8 Cyclic redundancy check calculation unit (CRC)

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a

configurable generator polynomial value and size.

Among other applications, CRC-based techniques are used to verify data transmission or

storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of

verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of

the software during runtime, to be compared with a reference signature generated at link-

time and stored at a given memory location.

3.9 Power supply management

3.9.1 Power supply schemes

• V

= 1.71 to 3.6 V: external power supply for I/Os (V

DDIO1

), the internal regulator and

the system analog such as reset, power management and internal clocks. It is provided

externally through VDD pins.

• V

DDA

= 1.62 V (ADCs/COMPs) / 1.8 (DAC/OPAMPs) to 3.6 V: external analog power

supply for ADCs, DAC, OPAMPs, Comparators and Voltage reference buffer. The V

DDA

voltage level is independent from the V

voltage.

• V

DDUSB

= 3.0 to 3.6 V: external independent power supply for USB transceivers. The

DDUSB

voltage level is independent from the V

voltage.

• V

BAT

= 1.55 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and

backup registers (through power switch) when V

is not present.

Note: When the functions supplied by V

DDA

or V

DDUSB

are not used, these supplies should

preferably be shorted to V

Note: If these supplies are tied to ground, the I/Os supplied by these power supplies are not 5 V

tolerant (refer to

Table 20: Voltage characteristics).

Note: V

DDIOx

is the I/Os general purpose digital functions supply. V

DDIOx

represents V

DDIO1

, with

DDIO1

= V

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