"Renesas RH850/F1KH-F1KM微控制器数据手册及用户手册详解"

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The RH850 F1KH-F1KM data manual provides detailed information about the RH850/F1KH and RH850/F1KM microcontrollers from Renesas Electronics Corp. This manual covers hardware specifications and features of the RH850 family of microcontrollers, offering a comprehensive overview of the product at the time of publication. The RH850/F1KH and RH850/F1KM microcontrollers are designed for use in automotive applications, providing high-performance processing capabilities for a wide range of automotive systems. The manual includes detailed technical specifications, pin assignments, memory configurations, and peripheral interfaces to help developers design and implement their systems effectively. All information provided in the manual is accurate at the time of publication but is subject to change by Renesas Electronics Corp. without notice. It is recommended that users check the latest information on the Renesas Electronics Corp. website for any updates or changes to the product specifications. Overall, the RH850 F1KH-F1KM data manual is a valuable resource for developers working with the RH850 family of microcontrollers, providing everything they need to know to utilize the capabilities of these powerful devices in their automotive applications.

2C.10.3.1 Alternative Function ................................................................................................ 507

2C.10.3.2 Control Registers .................................................................................................... 509

2C.10.4 Port 9 (P9) .......................................................................................................................... 511

2C.10.4.1 Alternative Function ................................................................................................ 511

2C.10.4.2 Control Registers .................................................................................................... 512

2C.10.5 Port 10 (P10) ...................................................................................................................... 514

2C.10.5.1 Alternative Function ................................................................................................ 514

2C.10.5.2 Control Registers .................................................................................................... 516

2C.10.6 Port 11 (P11) ...................................................................................................................... 518

2C.10.6.1 Alternative Function ................................................................................................ 518

2C.10.6.2 Control Registers .................................................................................................... 519

2C.10.7 Analog Port 0 (AP0) ........................................................................................................... 520

2C.10.7.1 Alternative Function ................................................................................................ 520

2C.10.7.2 Control Registers .................................................................................................... 521

2C.11 Port (Special I/O) Function Overview ........................................................................................... 522

2C.11.1 Special I/O after Reset ....................................................................................................... 522

2C.11.1.1 P8_6: RESETOUT ................................................................................................ 522

2C.11.1.2 JP0_0 to JP0_5: Debug Interface ........................................................................... 525

2C.11.1.3 FPDR(JP0_0), FPDT(JP0_1), FPCK(JP0_2): Flash Programmer ......................... 525

2C.11.1.4 Mode Pins ............................................................................................................... 525

2C.11.2 A/D Input Alternative I/O .................................................................................................... 526

2C.11.3 Special I/O Control ............................................................................................................. 527

2C.11.3.1 Direct I/O Control (PIPC) ........................................................................................ 527

2C.11.3.2 Input Buffer Control (PISn/JPIS0, JPISA0) ............................................................. 528

2C.11.3.3 Output Buffer Control (PDSC) ................................................................................ 530

2C.12 Noise Filter & Edge/Level Detector .............................................................................................. 532

2C.12.1 Port Filter Assignment ........................................................................................................ 532

2C.12.1.1 Input Pins that Incorporate Analog Filter Type A .................................................... 532

2C.12.1.2 Input Pins that Incorporate Analog Filter Type B .................................................... 533

2C.12.1.3 Input Pins that Incorporate Analog Filter Type C .................................................... 534

2C.12.1.4 Input Pins that Incorporate Digital Filter Type D ..................................................... 535

2C.12.1.5 Input Pins that Incorporate Digital Filter Type E ..................................................... 536

2C.12.2 Clock Supply for Port Filters .............................................................................................. 538

2C.13 Description of Port Noise Filter & Edge/Level Detection .............................................................. 539

2C.13.1 Overview ............................................................................................................................ 539

2C.13.1.1 Analog Filter Types ................................................................................................. 539

2C.13.1.2 Digital Filter Types .................................................................................................. 539

2C.13.2 Analog Filters ..................................................................................................................... 540

2C.13.2.1 Analog Filter Characteristic ..................................................................................... 540

2C.13.2.2 Analog Filter Control Registers ............................................................................... 540

2C.13.2.3 Analog Filter in Standby Mode ................................................................................ 540

2C.13.3 Digital Filters ...................................................................................................................... 543

2C.13.3.1 Digital Filter Characteristic ...................................................................................... 543

2C.13.3.2 Digital Filter Groups ................................................................................................ 544

2C.13.3.3 Digital Filters in Standby Mode ............................................................................... 544

2C.13.3.4 Digital Filter Control Registers ................................................................................ 545

2C.13.4 Filter Control Registers ...................................................................................................... 546

2C.13.4.1 FCLA0CTLm_<name> — Filter Control Register ................................................... 547

2C.13.4.2 DNFA<name>CTL — Digital Noise Elimination Control Register .......................... 548

2C.13.4.3 DNFA<name>EN — Digital Noise Elimination Enable Register ............................ 549

2C.13.4.4 DNFA<name>ENH — Digital Noise Elimination Enable H Register ...................... 550

2C.13.4.5 DNFA<name>ENL — Digital Noise Elimination Enable L Register ....................... 550

Section 3A CPU System of RH850/F1KH-D8 .............................................................. 551

3A.1 Overview ....................................................................................................................................... 551

3A.1.1 Block Configuration ............................................................................................................ 551

3A.2 CPU .............................................................................................................................................. 554

3A.2.1 Core Functions ................................................................................................................... 554

3A.2.1.1 Features .................................................................................................................. 554

3A.2.1.2 Register Set ............................................................................................................ 555

3A.2.1.3 Instruction ............................................................................................................... 592

3A.2.2 Buffers for Code Flash ....................................................................................................... 593

3A.2.2.1 Features .................................................................................................................. 593

3A.2.2.2 Function of Buffers .................................................................................................. 593

3A.2.2.3 Registers for Buffer Control .................................................................................... 594

3A.2.3 Inter-Processor Interrupts .................................................................................................. 595

3A.2.3.1 Inter-Processor Interrupt Control Registers ............................................................ 595

3A.2.4 Reliability Functions ........................................................................................................... 597

3A.2.4.1 PE Guard Function (PEG) ...................................................................................... 597

3A.2.4.2 PE’s Internal Peripheral Device Protection Function (IPG) .................................... 603

3A.2.4.3 System Error Generator Function (SEG) ................................................................ 610

3A.3 Inter-CPU Functions ..................................................................................................................... 615

3A.3.1 Processor Element Identifier .............................................................................................. 615

3A.3.2 Inter-Processor Interrupt Function ..................................................................................... 615

3A.3.3 Exclusive Control ............................................................................................................... 615

3A.3.3.1 Exclusive Control Register (G0MEVm; m = 0 to 31) .............................................. 615

3A.3.3.2 Operation of the LDL.W and STC.W Instructions ................................................... 617

3A.4 CPU2 Boot Up Operation ............................................................................................................. 618

3A.5 Notes............................................................................................................................................. 619

3A.5.1 Synchronization of Store Instruction Completion and Subsequent Instruction Execution . 619

3A.5.2 Ensure Coherency after Rewriting the Code Flash ........................................................... 620

3A.5.3 Access to Registers by Using Bit-Manipulation Instructions .............................................. 620

3A.5.4 Caution of Prefetching ....................................................................................................... 620

3A.5.5 Overwriting Context upon Acceptance of Multiple Exceptions .......................................... 620

Section 3BC CPU System of RH850/F1KM ......................................................................... 621

3BC.1 Overview ....................................................................................................................................... 621

3BC.1.1 Block Configuration ............................................................................................................ 621

3BC.2 CPU .............................................................................................................................................. 624

3BC.2.1 Core Functions ................................................................................................................... 624

3BC.2.1.1 Features .................................................................................................................. 624

3BC.2.1.2 Register Set ............................................................................................................ 625

3BC.2.1.3 Instruction ............................................................................................................... 662

3BC.2.2 Buffers for Code Flash ....................................................................................................... 663

3BC.2.2.1 Features .................................................................................................................. 663

3BC.2.2.2 Function of Buffers .................................................................................................. 663

3BC.2.2.3 Registers for Buffer Control .................................................................................... 664

3BC.2.3 Reliability Functions ........................................................................................................... 665

3BC.2.3.1 PE Guard Function (PEG) ...................................................................................... 665

3BC.2.3.2 PE’s Internal Peripheral Device Protection Function (IPG) .................................... 671

3BC.2.3.3 System Error Generator Function (SEG) ................................................................ 678

3BC.3 Notes............................................................................................................................................. 684

3BC.3.1 Synchronization of Store Instruction Completion and Subsequent Instruction Execution . 684

3BC.3.2 Ensure Coherency after Rewriting the Code Flash ........................................................... 685

3BC.3.3 Access to Registers by Using Bit-Manipulation Instructions .............................................. 685

3BC.3.4 Caution of Prefetching ....................................................................................................... 685

3BC.3.5 Overwriting Context upon Acceptance of Multiple Exceptions .......................................... 685

Section 4A Address Space of RH850/F1KH-D8 ........................................................... 686

4A.1 Address Space ............................................................................................................................. 686

4A.2 Address Space Viewed from Each Bus Master ............................................................................ 689

4A.2.1 Space in which Instructions can be Fetched ..................................................................... 689

4A.2.2 Data Space Accessible by CPU1 ....................................................................................... 689

4A.2.3 Data Space Accessible by CPU2 ....................................................................................... 689

4A.2.4 Data Space Accessible by DMA ........................................................................................ 689

4A.2.5 Data Space Accessible by Flexray .................................................................................... 689

4A.2.6 Data Space Accessible by ETNB ....................................................................................... 689

4A.2.7 Data Space Accessible by Each Bus Master ..................................................................... 690

4A.3 Peripheral I/O Address Map ......................................................................................................... 692

Section 4B Address Space of RH850/F1KM-S4 .......................................................... 700

4B.1 Address Space ............................................................................................................................. 700

4B.2 Address Space Viewed from Each Bus Master ............................................................................ 707

4B.2.1 Space in which Instructions can be Fetched ..................................................................... 707

4B.2.2 Data Space Accessible by CPU ......................................................................................... 707

4B.2.3 Data Space Accessible by DMA ........................................................................................ 707

4B.2.4 Data Space Accessible by Flexray .................................................................................... 707

4B.2.5 Data Space Accessible by ETNB ....................................................................................... 707

4B.2.6 Data Space Accessible by Each Bus Master ..................................................................... 708

4B.3 Peripheral I/O Address Map ......................................................................................................... 709

Section 4C Address Space of RH850/F1KM-S1 .......................................................... 716

4C.1 Address Space ............................................................................................................................. 716

4C.2 Address Space Viewed from Each Bus Master ............................................................................ 718

4C.2.1 Space in which Instructions can be Fetched ..................................................................... 718

4C.2.2 Data Space Accessible by CPU ......................................................................................... 718

4C.2.3 Data Space Accessible by Each Bus Master ..................................................................... 718

4C.3 Peripheral I/O Address Map ......................................................................................................... 719

Section 5 Write-Protected Registers ............................................................................... 725

5.1 Overview ....................................................................................................................................... 725

5.1.1 Functional Overview........................................................................................................... 725

5.1.2 Writing Procedure to Write-Protected Registers ................................................................ 725

5.1.3 Interrupt during Write Protection Unlock ............................................................................ 726

5.1.4 Emulation Break during Write Protection Unlock Sequence.............................................. 727

5.1.5 Write-Protection Target Registers ...................................................................................... 727

5.2 Registers ....................................................................................................................................... 735

5.2.1 List of Registers ................................................................................................................. 735

5.2.2 Details of Control Protection Cluster Registers ................................................................. 740

5.2.2.1 PROTCMDn — Protection Command Register ...................................................... 740

5.2.2.2 PROTSn — Protection Status Register .................................................................. 741

5.2.3 Details of Clock Monitor Protection Cluster Registers ....................................................... 742

5.2.3.1 CLMAnPCMD — CLMAn Protection Command Register ...................................... 742

5.2.3.2 CLMAnPS — CLMAn Protection Status Register .................................................. 743

5.2.3.3 PROTCMDCLMA — Clock Monitor Test Protection Command Register .............. 744

5.2.3.4 PROTSCLMA — Clock Monitor Test Protection Status Register ........................... 745

5.2.4 Details of Core Voltage Monitor Protection Cluster Registers ........................................... 746

5.2.4.1 PROTCMDCVM — Core Voltage Monitor Protection Command Register ............ 746

5.2.4.2 PROTSCVM — Core Voltage Monitor Protection Status Register ......................... 747

5.2.5 Details of Port Protection Cluster Registers ...................................................................... 748

5.2.5.1 PPCMDn — Port Protection Command Register ................................................... 748

5.2.5.2 PPROTSn — Port Protection Status Register ........................................................ 749

5.2.6 Details of Self-Programming Protection Cluster Registers ................................................ 750

5.2.6.1 FLMDPCMD — FLMD Protection Command Register ........................................... 750

5.2.6.2 FLMDPS — FLMD Protection Error Status Register .............................................. 751

Section 6 Operating Mode .............................................................................................. 752

Section 7A Exception/Interrupts of RH850/F1KH-D8 ................................................... 753

7A.1 Features of RH850/F1KH Exception/Interrupts ............................................................................ 753

7A.2 Interrupt Sources .......................................................................................................................... 756

7A.2.1 Interrupt Sources ................................................................................................................ 756

7A.2.1.1 FE Level Non-Maskable Interrupts ......................................................................... 756

7A.2.1.2 FE Level Maskable Interrupts ................................................................................. 756

7A.2.1.3 EI Level Maskable Interrupts .................................................................................. 758

7A.2.2 FE Level Non-Maskable Interrupt Sources ........................................................................ 770

7A.2.2.1 List of Registers ...................................................................................................... 770

7A.2.2.2 WDTNMIF — FENMI Factor Register .................................................................... 770

7A.2.2.3 WDTNMIFC — WDTNMI Factor Clear Register .................................................... 771

7A.2.3 FE Level Maskable Interrupt Sources ................................................................................ 772

7A.2.3.1 List of Registers ...................................................................................................... 772

7A.2.3.2 FEINTF — FEINT Factor Register .......................................................................... 772

7A.2.3.3 FEINTFMSK — FEINT Factor Mask Register ........................................................ 775

7A.2.3.4 FEINTFC — FEINT Factor Clear Register ............................................................. 778

7A.3 Edge/Level Detection .................................................................................................................... 781

7A.4 Interrupt Controller Control Registers ........................................................................................... 782

7A.4.1 List of Registers ................................................................................................................. 782

7A.4.2 ICxxx — EI Level Interrupt Control Registers .................................................................... 783

7A.4.3 IMRm — EI Level Interrupt Mask Registers (m = 0 to 11) ................................................. 785

7A.4.4 IBDxxx — EI Level Interrupt Binding Registers ................................................................. 786

7A.4.5 FNC — FE Level NMI Status Register ............................................................................... 796

7A.4.6 FIC — FE Level Maskable Interrupt Status Register ......................................................... 797

7A.5 EI Level Maskable Interrupt Select Register ................................................................................ 798

7A.5.1 List of Registers ................................................................................................................. 798

7A.5.2 SELB_INTC1 — INTC1 Interrupt Select Register ............................................................. 799

7A.6 Interrupt Function System Registers ............................................................................................ 801

7A.6.1 FPIPR — FPI Exception Interrupt Priority .......................................................................... 801

7A.6.2 ISPR — Priority of Interrupt being Serviced ...................................................................... 801

7A.6.3 PMR — Interrupt Priority Masking ..................................................................................... 801

7A.6.4 ICSR — Interrupt Control Status ........................................................................................ 801

7A.6.5 INTCFG — Interrupt Function Setting ................................................................................ 801

7A.7 Operation when Acknowledging an Interrupt ............................................................................... 802

7A.7.1 Exception Source Codes for Different Types of SYSERR Exceptions .............................. 804

7A.8 Return from Interrupts ................................................................................................................... 805

7A.9 Interrupt Operation ........................................................................................................................ 806

7A.9.1 Interrupt Mask Function of EI Level Maskable Interrupt (EIINT) ....................................... 806

7A.9.2 Interrupt Priority Level Judgment ....................................................................................... 806

7A.9.2.1 Comparison with the Priority Level of the Interrupt Currently being Handled ......... 807

7A.9.2.2 Masking through Priority Mask Register (PMR) ..................................................... 807

7A.9.2.3 The Requested Interrupt Source with the Highest Priority Level is Selected ......... 807

7A.9.2.4 Interrupt Suspended by CPU .................................................................................. 807

7A.9.3 Interrupt Request Acknowledgement Conditions and the Priority ..................................... 811

7A.9.4 Exception Priority of Interrupts and the Priority Mask ........................................................ 811

7A.9.5 Interrupt Priority Mask ........................................................................................................ 811

7A.9.6 Priority Mask Function........................................................................................................ 811

7A.9.7 Exception Management ..................................................................................................... 811

7A.9.8 Inter-Processor Interrupts .................................................................................................. 812

7A.9.9 Broadcast Function (Broadcast Communication Function) ............................................... 812

7A.9.9.1 Example of Operation ............................................................................................. 813

7A.9.9.2 Inter-Processor Interrupt Flow ................................................................................ 814

7A.10 Exception Handler Address .......................................................................................................... 815

7A.10.1 Direct Vector Method ......................................................................................................... 816

7A.10.2 Table Reference Method ................................................................................................... 818

Section 7BC Exception/Interrupts of RH850/F1KM ............................................................. 820

7BC.1 Features of RH850/F1KM Exception/Interrupts ........................................................................... 820

7BC.2 Interrupt Sources .......................................................................................................................... 822

7BC.2.1 Interrupt Sources ................................................................................................................ 822

7BC.2.1.1 FE Level Non-Maskable Interrupts ......................................................................... 822

7BC.2.1.2 FE Level Maskable Interrupts ................................................................................. 822

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