Lattice DDR3 SDRAM Controller IP Core用户指南概述

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本资源是Lattice半导体公司发布的"Double Data Rate (DDR3) SDRAM Controller IP Core用户指南"（IPUG80 Version 1.9，发布日期：2016年10月）。该指南详细阐述了针对DDR3 SDRAM控制器IP Core的使用方法和技术特性，旨在帮助设计者充分利用这款高性能的内存接口控制器。 1. **简介**（Chapter 1）：快速概述了IP Core的主要特点，包括适用于DDR3标准的高速数据传输能力、高效能和低功耗设计。它旨在简化系统集成，并确保与各种DDR3 SDRAM模块兼容。 2. **功能描述**（Chapter 2）： - **DDR3 MC Module**：这部分解释了控制器如何与内存模块（MC）交互，包括命令解码逻辑，用于处理不同类型的内存操作指令。 - **命令应用逻辑**：详细说明了IP Core如何解析接收到的命令信号，并执行相应的内存操作，如写入、读取和刷新操作。 - **On-Die Termination**：介绍了控制器内置的终端匹配电路，用于优化信号完整性，确保数据在不同引脚上的正确接收。 - **DDR3 PHY Module**：描述了物理层模块，负责与内存模块的物理连接，包括信号时钟同步和信号质量监控。 - **初始化模块**：说明了控制器的初始化过程，确保在启动时正确设置工作模式和配置参数。 - **Write Leveling** 和 **Read Training**：针对特定型号的设备（ECP5和Lattice ECP3），提供了写入平滑技术和读取训练的使用指导。 - **Data Path Logic**：阐述了数据传输路径的实现，确保数据在控制器和内存之间的高效交换。 - **信号描述**：给出了接口中涉及的关键信号定义，帮助设计者理解信号的电气特性和时序规范。 3. **本地用户接口**：用户可以通过这个接口控制IP Core的工作模式、配置和错误检测，增强了可编程灵活性。 4. **模式寄存器编程**：强调了如何通过设置不同的寄存器来调整控制器的工作模式，以适应不同应用场景的需求。 5. **其他**：指南还涵盖了用户命令的具体使用，如WRITE、WRITEA、READ和READA操作，以及REFRESH支持等关键功能。这份用户指南为设计者提供了一个全面的指南，让他们能够充分理解和利用Lattice的DDR3 SDRAM控制器IP Core，实现高性能内存系统的构建。在实际应用中，设计者需要遵循指南中的指导，确保正确配置和操作IP Core，以达到最佳性能和稳定性。

Functional Description

IPUG80_1.9, October 2016 11 DDR3 SDRAM Controller IP Core User’s Guide

multiple trials. If there is any failure, the memory controller shifts the READ signal position and tries again until it

detects no BURSTDET failure.

The memory controller stores the delay value of the successful position of the READ signal for each DQS group. It

uses these delay values during a normal read operation to correctly detect the preamble first, followed by the gen-

eration of DATAVALID signal.

Selecting READ_PULSE_TAP Value (Only for LatticeECP3 Device)

For every read operation, the DDR3 I/O primitives must be initialized at the appropriate time to identify the incom-

ing DQS preamble in order to generate the data valid signal. For this purpose the controller internally generates a

signal called dqs_read in such a way that this signal’s trailing edge is positioned within the incoming DQS preamble

window.

Due to PCB routing delays, DIMM module routing delays and routing delays within the FPGA, the incoming DQS

signal’s delay varies from board to board. To compensate for this variability in DQS delay, the controller shifts the

internal signal dqs_read in such a way to position it within the preamble time.

Each shift (step) moves the dqs_read signal by one half period of the eclk (1.25ns for 400MHz memory clock).

A port, read_pulse_tap, is provided in the Core top level file ddr3_sdram_mem_top_wrapper.v for the user to load

the shift count for each DQS group. Each DQS group is assigned a 3-bit shift count value in this port, starting with

LSB 3 bits for DQS_0. This count can be any value from 0 to 7.

For the core to work properly on the board, it is recommended that the dqs_read signal be shifted by two steps for

UDIMMs, by four steps for RDIMMs or by one step for on-board memory. Since the Eval simulation environment is

provided without the PCB and FPGA internal routing delays, the recommended values for Eval simulation are: zero

steps for UDIMMs, two steps for RDIMMs or zero steps for on-board memory.

A parameter READ_PULSE_TAP in ddr_p_eval\testbench\tests\ecp3\tb_config_params.v is made available to the

user as an example. This parameter may be loaded to the port read_pulse_tap with appropriate values for simula-

tion and synthesis.

In almost all cases the recommended value is good enough for stable read operations on the board and it is highly

unlikely that the user has to change this value. If there are frequent read errors on the board, the user should try

adjusting the shift count value loaded to the port read_pulse_tap.

Should there be a need to change the READ_PULSE_TAP value, it is suggested that the user starts with changing

the value of DQS7 groups first and then move to adjacent group, if required.

Note: The DDR3 memory controller may fail to generate or improperly generate the read_data_valid signal if the

parameter READ_PULSE_TAP is not loaded to the read_pulse_tap input port or the values are not correct.

Data Path Logic

The Data Path Logic (DPL) block interfaces with the DDR3 I/O modules and is responsible for generating the read

data and read data valid signals during read operations. This block implements all the logic needed to ensure that

the data write/read to and from the memory is transferred to the local user interface in a deterministic and coherent

manner.

Functional Description

IPUG80_1.9, October 2016 12 DDR3 SDRAM Controller IP Core User’s Guide

Signal Descriptions

Table 2-1 describes the user interface and memory interface signals at the top level.

Table 2-1. DDR3 SDRAM Memory Controller Top-Level I/O List

Port Name

Active

State I/O Description

clk_in N/A Input Reference clock to the PLL of the CSM block.

Clock Synchronization Logic (CSM) Interface

sclk N/A Input

System clock used by controller’s core module. User may use

this clock for DDR3 controller interface logic.

eclk N/A Input

Edge clock used by controller’s PHY module. Usually twice the

Frequency of sclk.

sclk2x N/A Input

High speed system clock used by controller’s PHY module.

Usually twice the Frequency of sclk.

wl_rst_datapath High Input

Signal from the PHY to the CSM module triggering a reset to

the DDR primitive. If multiple PHY IPs are implemented in a

design, use an AND gate to feed the wl_rst_datapath signals

from all PHY IPs and connect the output of the AND gate to the

CSM module.

dqsbufd_rst High Output Signal from CSM module to the PHY to reset the DDR primitive.

clocking_good High Input Signal from CSM module indicating stable clock condition.

Local User Interface

rst_n Low Input

Asynchronous reset. By default setting, this signal resets the

entire IP core and the DDR3 memory when asserted. Refer to

“Reset Handling” on page 51 for more details.

mem_rst_n Low Input

Asynchronous reset signal from user to reset the memory

device only. This signal will not reset the memory controller.

Refer to “Reset Handling” on page 51 for more details.

init_start High Input

Initialization start request. Should be asserted to initiate mem-

ory initialization either right after the power-on reset or before

sending the first user command to the memory controller.

Refer to “Initialization Control” on page 14 for more details.

cmd[3:0] N/A Input

User command input to the memory controller. Refer to “User

Commands” on page 16 for available commands.

cmd_valid High Input

Command and address valid input. When asserted, the addr,

cmd, ofly_burst_len and cmd_burst_cnt inputs are considered

valid. Refer to “Command and Address” on page 15 for more

details.

addr[ADDR_WIDTH-1:0] N/A Input

User read or write address input to the memory controller.

Refer the section “Local-to-Memory Address Mapping” for fur-

ther details.

cmd_burst_cnt[4:0] N/A Input

Command burst count input – Indicates the number of times a

given read or write command is to be repeated by the controller

automatically. Controller also generates the address for each

repeated command sequentially as per the burst length of the

command. Burst range is from 1 to 32 and “0” indicates 32 rep-

etitions

ofly_burst_len N/A Input

On-the-fly burst length for current command.

0 = BC4, 1 = BL8.

This input is valid only if Mode Reg0 is set for on-the-fly mode.

If set, this input is sampled when cmd_valid and cmd_rdy are

high.

write_data[DSIZE-1:0] N/A Input

Write data input from user logic to the memory controller. The

user side write data width is four times the memory databus.

Functional Description

IPUG80_1.9, October 2016 13 DDR3 SDRAM Controller IP Core User’s Guide

data_mask[(DSIZE/8)[1:0] High Input

Data mask input for write data. Each bit masks a correspond-

ing byte of local write data.

ext_auto_ref High Input

Refresh request from user – This signal is available only when

the External Auto Refresh Port is selected in the GUI.

init_done High Output

Initialization done output – Asserted for one clock period after

the core completes memory initialization and write leveling.

When sampled high, the input signal init_start must be immedi-

ately deasserted at the same edge of the sampling clock. Refer

to “Initialization Control” on page 14 for more details.

cmd_rdy High Output

Command ready output – When asserted, indicates that the

core is ready to accept the next command and the correspond-

ing address. This cmd_rdy signal is active for one clock period.

datain_rdy High Output

Data ready output – When asserted, indicates the core is

ready to receive the write data.

read_data[DSIZE-1:0] N/A Output Read data output from memory controller to the user logic.

read_data_valid High Output

Read data valid output – When asserted, indicates the data on

the read_data bus is valid.

ext_auto_ref_ack High Output

Completion of memory refresh in response to ext_auto_ref sig-

nal assertion. This pin is available only when the External Auto

Refresh Port is selected in the GUI.

wl_err High Output

Write leveling error. Indicates failure in write leveling. The con-

troller will not work properly if there is a write leveling error.

This signal should be checked when init_done signal is

asserted.

rt_err High Output

Read Training error. Indicates failure in Read Training process.

The controller will not work properly if there is a Read Training

error. This signal should be checked when init_done signal is

asserted. (Only for ECP5 DDR3 IP.)

read_pulse_tap [3*(`DQS_WIDTH)

-1:0]

High Input

Read pulse tap – Count value of 0 to 7 by which the controller's

internal read pulse signal, dqs_read, is to be shifted for proper

read_data_valid signal generation. Default value is 2. Three

bits are allocated for each DQS. (Only for LatticeECP3 DDR3

IP.)

DDR3 SDRAM Memory Interface

em_ddr_reset_n Low Output

Asynchronous reset signal from the controller to the memory

device. Asserted by the controller for the duration of power on

reset or active rst_n or active mem_rst_n. Refer to “Reset Han-

dling” on page 51 for more details.

em_ddr_clk[CLKO_WIDTH-1:0] N/A Output Up to 400 MHz memory clock generated by the controller.

em_ ddr_clk_n[CLKO_WIDTH-1:0] N/A Output

400 MHz complimentary memory clock generated by the con-

troller.

em_ ddr_cke[CKE_WIDTH-1:0] High Output Memory clock enable generated by the controller.

em_ ddr_addr[ROW_WIDTH-1:0] N/A Output

Memory address bus – multiplexed row and column address

for the memory.

em_ ddr_ba[2:0] N/A Output Memory bank address.

em_ ddr_data[DATA_WIDTH-1:0] N/A In/Out Memory bi-directional data bus.

em_ ddr_dm[(DATA_WIDTH/8)-1:0] High Output

DDR3 memory write data mask – to mask the byte lanes for

byte-level write.

em_ ddr_dqs[DQS_WIDTH-1:0] N/A In/Out Memory bi-directional data strobe.

em_ ddr_dqs_n[DQS_WIDTH-1:0] N/A In/Out Memory complimentary bi-directional data strobe

em_ ddr_cs_n[CS_WIDTH-1:0] Low Output Memory chip select.

Table 2-1. DDR3 SDRAM Memory Controller Top-Level I/O List (Continued)

Port Name

Active

State I/O Description

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