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Functional Description
IPUG80_1.9, October 2016 13 DDR3 SDRAM Controller IP Core User’s Guide
data_mask[(DSIZE/8)[1:0] High Input
Data mask input for write data. Each bit masks a correspond-
ing byte of local write data.
ext_auto_ref High Input
Refresh request from user – This signal is available only when
the External Auto Refresh Port is selected in the GUI.
init_done High Output
Initialization done output – Asserted for one clock period after
the core completes memory initialization and write leveling.
When sampled high, the input signal init_start must be immedi-
ately deasserted at the same edge of the sampling clock. Refer
to “Initialization Control” on page 14 for more details.
cmd_rdy High Output
Command ready output – When asserted, indicates that the
core is ready to accept the next command and the correspond-
ing address. This cmd_rdy signal is active for one clock period.
datain_rdy High Output
Data ready output – When asserted, indicates the core is
ready to receive the write data.
read_data[DSIZE-1:0] N/A Output Read data output from memory controller to the user logic.
read_data_valid High Output
Read data valid output – When asserted, indicates the data on
the read_data bus is valid.
ext_auto_ref_ack High Output
Completion of memory refresh in response to ext_auto_ref sig-
nal assertion. This pin is available only when the External Auto
Refresh Port is selected in the GUI.
wl_err High Output
Write leveling error. Indicates failure in write leveling. The con-
troller will not work properly if there is a write leveling error.
This signal should be checked when init_done signal is
asserted.
rt_err High Output
Read Training error. Indicates failure in Read Training process.
The controller will not work properly if there is a Read Training
error. This signal should be checked when init_done signal is
asserted. (Only for ECP5 DDR3 IP.)
read_pulse_tap [3*(`DQS_WIDTH)
-1:0]
High Input
Read pulse tap – Count value of 0 to 7 by which the controller's
internal read pulse signal, dqs_read, is to be shifted for proper
read_data_valid signal generation. Default value is 2. Three
bits are allocated for each DQS. (Only for LatticeECP3 DDR3
IP.)
DDR3 SDRAM Memory Interface
em_ddr_reset_n Low Output
Asynchronous reset signal from the controller to the memory
device. Asserted by the controller for the duration of power on
reset or active rst_n or active mem_rst_n. Refer to “Reset Han-
dling” on page 51 for more details.
em_ddr_clk[CLKO_WIDTH-1:0] N/A Output Up to 400 MHz memory clock generated by the controller.
em_ ddr_clk_n[CLKO_WIDTH-1:0] N/A Output
400 MHz complimentary memory clock generated by the con-
troller.
em_ ddr_cke[CKE_WIDTH-1:0] High Output Memory clock enable generated by the controller.
em_ ddr_addr[ROW_WIDTH-1:0] N/A Output
Memory address bus – multiplexed row and column address
for the memory.
em_ ddr_ba[2:0] N/A Output Memory bank address.
em_ ddr_data[DATA_WIDTH-1:0] N/A In/Out Memory bi-directional data bus.
em_ ddr_dm[(DATA_WIDTH/8)-1:0] High Output
DDR3 memory write data mask – to mask the byte lanes for
byte-level write.
em_ ddr_dqs[DQS_WIDTH-1:0] N/A In/Out Memory bi-directional data strobe.
em_ ddr_dqs_n[DQS_WIDTH-1:0] N/A In/Out Memory complimentary bi-directional data strobe
em_ ddr_cs_n[CS_WIDTH-1:0] Low Output Memory chip select.
Table 2-1. DDR3 SDRAM Memory Controller Top-Level I/O List (Continued)
Port Name
Active
State I/O Description